Non-Volatile Memory Controller Reactive Power Management

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Solution Overview

Problem

Memory controllers in solid-state data storage systems face power limitations and processing delays, leading to suboptimal performance due to unmanaged power consumption and command backlogs.

Innovation Solution

Implementing a system with a central controller and channel controllers that dynamically adjust clock frequencies based on command queue backlog information to maintain pending memory commands below a predetermined threshold, using dynamic frequency scaling to optimize power consumption and processing throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory controllers operate at full speed to process memory commands, then productivity is improved, but power consumption increases beyond acceptable limits

Engineering Contradiction:
Improvememory command processing speedVSAvoidpower consumption of memory controllers
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent implements dynamic frequency scaling that adjusts the clock frequency of memory controllers based on real-time command queue backlog levels. When command queues are empty or near-empty, the controller reduces its operating frequency to minimize power consumption. When command queues accumulate backlog, the controller increases frequency to maintain productivity. This dynamic adjustment resolves the contradiction by making the operating speed adaptive rather than fixed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters (clock frequency) of memory controllers based on workload conditions. By monitoring command queue depth and adjusting frequency accordingly, the system optimizes the balance between processing speed and power consumption, allowing full speed only when necessary to clear backlogs while operating at reduced speed during low-utilization periods.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If memory controllers reduce operating speed to lower power consumption, then power usage is improved, but command processing backlog increases

Engineering Contradiction:
Improvepower consumption of memory controllersVSAvoidmemory command processing throughput
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent implements a feedback mechanism where the memory controller continuously monitors the backlog level in its command queues and uses this information to adjust its operating frequency. When backlog exceeds a threshold, the controller increases frequency to clear the queue; when backlog is low, it reduces frequency to save power. This closed-loop control ensures that productivity is maintained only when necessary, resolving the contradiction between power savings and backlog accumulation.

Inventive Principle:
Principle #23Feedback

3Productivity

If multiple commands are executed in parallel across multiple channels, then productivity is improved, but power consumption and processing complexity increase

Engineering Contradiction:
Improveparallel command execution capabilityVSAvoidpower consumption of memory controllers
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent divides the memory system into multiple independent channel controllers, each with its own command queue and frequency control. This segmentation allows the system to activate and adjust the frequency of individual channels based on their specific workload, rather than forcing all channels to operate at high frequency simultaneously. Only channels with active command backlogs consume high power, reducing overall system power consumption while maintaining parallel processing capability when needed.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10514748B2Reactive power management for non-volatile memory controllers
Publication Date: 2019.12.24 SANDISK TECHNOLOGIES LLC
  • US10514748B2 patent drawing
  • US10514748B2 patent drawing
  • US10514748B2 patent drawing

AI summary

Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.