NVM Controller Prefetching AIT Entries to Reduce Cache Misses
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Solution Overview
Problem
Conventional DRAM memories are volatile, leading to data loss when powered off and require frequent refresh operations, resulting in high power consumption, while non-volatile memories offer advantages like high storage density and low power consumption but suffer from slow access times due to immature access technologies.
Innovation Solution
A method and system that cache a to-be-accessed address indirection table entry to an AIT cache to reduce memory access delays by prefetching AIT entries when the processor accesses the page table, thereby reducing subsequent AIT cache misses and enhancing data access speed in non-volatile memory systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If non-volatile memory is used instead of DRAM, then power consumption is reduced and data retention is improved, but memory access speed deteriorates
Solution Approach 1:
The patent implements a page table prefetching mechanism that proactively loads page table entries into the TLB before they are actually needed by the processor. When the memory controller detects a page table access, it predicts future page table accesses and prefetches those entries in advance, so that when the processor needs them, they are already cached, eliminating the slow NVM access for these predictive loads.
Solution Approach 2:
The patent segments the address translation process into two distinct paths: a fast path for regular memory accesses that use the TLB cache, and a slow path for page table accesses that directly access NVM. By separating these operations and optimizing the fast path through prefetching, the system minimizes the impact of slow NVM access on overall performance while maintaining power efficiency.
2Speed
If DRAM is used for memory, then access speed is improved, but power consumption increases due to frequent refresh operations
Solution Approach 1:
The patent extracts the refresh operation requirement from the memory system by transitioning from volatile DRAM to non-volatile memory. NVM inherently retains data without power, eliminating the need for periodic refresh operations. The system takes out the refresh mechanism entirely and replaces it with a prefetching-based performance optimization approach.
3Duration of action of stationary object
If DRAM is used for memory, then data retention is improved, but data loss occurs when power is turned off
Solution Approach 1:
The patent uses volatile DRAM as a temporary, disposable cache layer (TLB) for address translations. This short-living cached data structure provides fast access during operation but is naturally lost on power-off. However, the underlying NVM provides persistent storage, creating a hierarchical system where the volatile cache improves performance while the non-volatile base ensures data reliability.
Data Source
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AI summary
A method, an apparatus, and a system for accessing a non-volatile memory are disclosed. The method includes: receiving, by an NVM controller, a first access request from a processor; determining, based on first address information carried in the first access request, whether the first access request is used to access a page table; and if the first access request is used to access the page table, reading, by the NVM controller, a page table entry indicated by the first address information, obtaining, based on second address information recorded in the page table entry, an AIT entry corresponding to the second address information from an AIT, and caching the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches a to-be-accessed AIT entry corresponding to the second address information from the AIT, and caches the prefetched AIT entry to the AIT cache. In this way, subsequent AIT cache misses are reduced, thereby increasing a data access speed of the NVM.