NVM Controller Register Access Arbitration
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Solution Overview
Problem
The development and design of non-volatile memory (NVM) data storage controllers face challenges when standard changes occur, requiring costly and time-consuming redesigns of application-specific integrated circuits (ASICs) to accommodate new features, as existing solutions necessitate hardware modifications for each standard revision, leading to inefficiencies and high expenses.
Innovation Solution
Implementing a method where a data storage controller uses software and/or firmware to emulate hardware registers, allowing for the execution of register access requests using a processor instead of hardware, thereby enabling support for new standard features without modifying the hardware, thus allowing for future standard changes to be implemented without hardware redesigns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware memory registers are used to execute register access requests, then execution speed is improved, but adaptability to standard changes deteriorates
Solution Approach 1:
The register access request execution is segmented into two paths: hardware memory register execution for standard requests and processor execution for non-standard requests. This segmentation allows the system to maintain fast hardware execution for common operations while routing novel or modified standard requests to the processor, thereby resolving the contradiction between speed and adaptability.
Solution Approach 2:
The determination component acts as an intermediary between the host device and the execution components. It receives register access requests, determines whether they correspond to executable hardware memory registers, and routes them appropriately. This intermediary enables the system to maintain hardware performance while adapting to standard changes through software-controlled routing decisions.
2Adaptability or versatility
If hardware is redesigned to accommodate new standard features, then compliance with new standards is achieved, but development cost and time increase
Solution Approach 1:
Instead of physically redesigning hardware memory registers for each new standard feature, the system creates a determination component that identifies and routes requests for new features to the processor. This virtual copying approach allows the hardware to remain unchanged while the processor handles the functionality of new standard features, dramatically reducing development time and cost.
Solution Approach 2:
The system transitions from a static hardware configuration to a dynamic execution model where the determination component can adaptively route requests based on the current standard version and available processor capabilities. This dynamic approach allows the system to comply with evolving standards without physical hardware changes, reducing both development time and cost.
3Device complexity
If hardware memory registers are used for all register access requests, then device complexity is reduced, but ability to support new features without hardware changes deteriorates
Solution Approach 1:
The controller structure is segmented into hardware memory registers for standard operations and a processor for advanced operations. The determination component segments the request handling logic, routing simple requests to hardware and complex or new requests to the processor. This segmentation maintains relative simplicity for common operations while enabling software-based support for new features.
Solution Approach 2:
The determination component provides universal functionality by handling both hardware register access requests and processor-based requests through a unified interface. It universally determines whether each request should be executed by hardware or software, allowing the system to support multiple execution modes without increasing overall structural complexity.
Data Source
AI summary
The present disclosure describes technologies and techniques for use by a data storage controller (such as a non-volatile memory (NVM) controller) to emulate hardware registers in software and/or firmware. In illustrative examples, an arbiter of the NVM controller arbitrates inbound register accesses from a host. Regular register accesses from the host are directed by the arbiter along a regular hardware read path within the NVM controller to physical memory registers. Other transactions (e.g. writes to, or reads from, an undefined or reserved address space) are instead directed by the arbiter to the processor of the NVM controller for handling by software running on the processor (and/or by firmware). In this manner, new hardware registers added to an NVM standard may be implemented by software and/or firmware rather than hardware. Hence, the NVM controller may comply with new standard requirements without changing the hardware. NVMe examples are provided.