Non-Volatile Memory Controller Single Chip Enable Pin
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Solution Overview
Problem
Conventional non-volatile memory storage systems require multiple chip enable pins for multi-channel access, leading to increased size and cost, particularly in portable applications where miniaturization is essential.
Innovation Solution
A non-volatile memory storage system that enables multi-channel and single channel access using a single chip enable pin, allowing simultaneous or selective access to multiple non-volatile memory chips without altering data in unaccessed chips, through a controller connected via I/O buses and a control bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple chip enable pins are used to enable multiple non-volatile memory chips for multi-channel access, then the data accessing amount is increased, but the number of pins and system size is increased
Solution Approach 1:
The single chip enable pin is designed to serve multiple non-volatile memory chips simultaneously. The controller enables multiple chips through one shared chip enable pin, and then uses different I/O buses to access different chips, making the chip enable pin universal rather than dedicated to a single chip.
Solution Approach 2:
Multiple chip enable functions are merged into a single chip enable pin. Instead of having separate enable pins for each memory chip, the patent combines the enable control into one shared pin that can activate multiple chips at once, reducing the total pin count while maintaining multi-channel access capability.
2Ease of operation
If multiple chip enable pins are used for each non-volatile memory chip, then single channel access to specific chips is enabled, but the system cost and size are increased
Solution Approach 1:
The single chip enable pin provides universal enable capability for all connected non-volatile memory chips. The controller can selectively enable specific chips or multiple chips simultaneously through this single pin, and then use different I/O buses to access them individually, maintaining single channel access capability without requiring dedicated enable pins for each chip.
Solution Approach 2:
The controller acts as an intermediary between the single chip enable pin and multiple memory chips. It receives the enable signal on the single pin, distributes it to the appropriate chips, and manages the I/O bus connections, allowing selective access without direct one-to-one pin-to-chip mapping.
3Productivity
If multiple I/O buses are used for multi-channel access to multiple memory chips, then data transmission capacity is increased, but the number of pins and system complexity is increased
Solution Approach 1:
The system segments the data transmission paths by creating separate I/O buses for different memory chips. Each I/O bus is dedicated to specific chips, allowing simultaneous independent data transmission to multiple chips through parallel buses, thereby increasing overall data transmission capacity while maintaining organized separation of data paths.
Data Source
AI summary
A non-volatile memory storage system including a transmission interface, a memory module, and a controller is provided. The memory module includes first and second non-volatile memory chips. The first and the second non-volatile memory chips can be simultaneously enabled by receiving a chip enable signal from the controller via a chip enable pin. When the controller performs a multichannel access, the controller provides an access instruction to the first and second non-volatile memory chip, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal. When the controller performs a single channel access, the controller provides the access signal to one of the first and second non-volatile memory chips, and provides a non-access instruction to the other one, after enabling the first non-volatile memory chip and the second non-volatile memory chip with the chip enable signal.