Non-Volatile Memory Controller Sub Mapping Table Queuing

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Solution Overview

Problem

The increasing size of flash memory devices poses a challenge in managing large logical-to-physical address mapping tables, requiring efficient use of limited DRAM to speed up access and updates, while maintaining high data storage performance.

Innovation Solution

Implementing a data storage device with a non-volatile memory, a controller, and a temporary storage that uses a waiting queue to manage sub mapping tables, allowing for caching of write data and queuing of write commands until the sub mapping table is fully downloaded, enabling continuous operation and high performance without pausing for table downloads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the sub mapping table is completely downloaded to the temporary storage before processing write commands, then the data storage performance is maintained, but the device must pause operation during the download process, reducing productivity

Engineering Contradiction:
Improvedata storage performanceVSAvoiddevice operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by queuing write commands in advance (before the sub mapping table is fully downloaded) and caching write data temporarily. This allows the system to prepare data and commands ahead of time, so that when the sub mapping table download completes, the controller can immediately process the queued commands without pausing operation, thus maintaining both performance and productivity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a waiting queue as an intermediary mechanism between the host and the controller. The waiting queue holds write commands temporarily, allowing the system to decouple the command submission from the actual execution. This intermediary buffer enables continuous operation during sub mapping table downloads while ensuring commands are processed in order once the download completes

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the controller waits for the sub mapping table to be fully downloaded before caching write data, then data integrity is ensured, but the device loses valuable time, reducing productivity

Engineering Contradiction:
Improvedata integrityVSAvoiddownload waiting time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system takes preliminary action by caching write data in the temporary storage before the sub mapping table download is complete. The controller queues the write command and caches the write data in advance, so that when the download finishes, the data is already ready for immediate programming, eliminating the need to wait during the download process while maintaining data integrity through proper queuing mechanisms

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the temporary storage is used to cache write data before the sub mapping table is ready, then the device maintains high throughput, but the temporary storage space must be managed carefully to avoid conflicts

Engineering Contradiction:
Improvedata throughputVSAvoidtemporary storage management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the temporary storage into distinct functional areas: a waiting queue for write commands and a data cache area for write data. This segmentation allows independent management of command queuing and data caching operations, reducing conflicts and simplifying the management logic while enabling high throughput by allowing both commands and data to be prepared simultaneously

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11126558B2Data storage device and control method for non-volatile memory
Publication Date: 2021.09.21 SILICON MOTION INC
  • US11126558B2 patent drawing
  • US11126558B2 patent drawing
  • US11126558B2 patent drawing

AI summary

A high-performance data storage device is disclosed. A controller updates a sub mapping table on the temporary storage in response to a write command of the non-volatile memory issued by a host. The mapping sub-table corresponds to a logical group involved in the write command and is downloaded from the non-volatile memory. When the mapping sub-table has not been completely downloaded to the temporary storage memory, the controller pushes the write command to a waiting queue to avoid dragging the performance of the data storage device.