Non-Volatile Memory Data Path Control for Latency Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As speeds increase for non-volatile memory and data buses, data path latency becomes a significant issue, particularly when accessing smaller data units, leading to inefficiencies in storage operations within non-volatile memory systems.
Innovation Solution
The implementation of a data path control mechanism that includes an internal controller and buffer within a memory die, which delays storage operations when the internal data pipeline and buffer are full, allowing the pipeline to function as an extension of the buffer and reducing latency by preventing buffer overflows and avoiding the need for additional on-die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the internal data pipeline and buffer are made larger to handle higher speeds and smaller data units, then data path latency is reduced, but the on-die area increases
Solution Approach 1:
The patent implements dynamic control of the data pipeline by using a controller that monitors buffer fullness and dynamically halts or resumes address dispatch based on pipeline status. This dynamic adjustment allows the system to achieve low latency performance when needed while avoiding the need for permanently oversized buffers, thus reducing on-die area.
Solution Approach 2:
The patent introduces an intermediary controller that sits between the address dispatch mechanism and the data pipeline. This controller acts as a mediator that coordinates between the buffer status and pipeline operation, enabling efficient data flow management without requiring additional buffer capacity, thereby resolving the area-latency tradeoff.
2Reliability
If the buffer size is increased to prevent overflows at higher speeds, then reliability is improved, but the on-die area increases
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors the fullness status of the buffer and pipeline, and adjusts address dispatch accordingly. When the buffer is full or pipeline is stalled, the controller halts dispatch to prevent overflow; when resources are available, it resumes dispatch. This feedback-based control ensures reliability without requiring oversized buffers.
Solution Approach 2:
The controller performs preliminary checks of buffer and pipeline status before dispatching addresses. By checking availability in advance and halting dispatch when full, the system prevents overflow conditions before they occur, maintaining reliability without needing excessive buffer capacity.
Data Source
AI summary
Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.