Non-Volatile Memory on DDR Channel for Cost-Performance Tradeoff
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current information handling systems face challenges in optimizing performance, cost, power, and reliability due to limited space for new features, with existing memory solutions like DRAM being expensive and solid-state drives having high latency and processing overhead, while users often underutilize server DIMM sockets.
Innovation Solution
The implementation of non-volatile memory (NVM) devices such as Phase Change Memory (PCM) on a double data rate (DDR) memory channel, allowing for direct reads and indirect writes, enabling efficient use of system resources and optimizing system configurations based on user requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM is used for main memory, then performance is improved, but cost increases
Solution Approach 1:
The memory system is segmented into two tiers: volatile memory (DRAM) for performance-critical operations and non-volatile memory (NVM) for cost-effective storage. The memory controller manages both types of memory, allowing the system to leverage the speed of DRAM for frequently accessed data while using the lower-cost NVM for less frequently accessed data, thus resolving the contradiction between performance and cost.
2Ease of manufacture
If SSDs are used for storage, then cost is reduced, but latency increases
Solution Approach 1:
The patent introduces a memory buffer as an intermediary between the host processor and NVM devices. This buffer temporarily stores data during write operations, allowing the host to continue processing without waiting for NVM write completion. The buffer mediates the latency between the fast host processor and the slower NVM, effectively reducing the perceived access time while maintaining the cost advantages of NVM.
3Quantity of substance
If all DIMM sockets are filled with DRAM, then system capacity is maximized, but volume utilization is inefficient
Solution Approach 1:
The system allows different DIMM sockets to have different memory types populated based on local requirements. Some sockets can contain DRAM for performance-critical applications, while others can contain NVM for cost-effective capacity. This local differentiation optimizes the volume utilization by filling available sockets with the most appropriate memory type rather than uniformly populating all sockets with DRAM.
4Volume of moving object
If NVM devices are added to DDR channel, then volume utilization is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle both DRAM and NVM devices through a unified interface. It can detect the type of memory device present in each DIMM socket and automatically configure appropriate access patterns and control signals. This universal approach allows the system to accommodate multiple memory types without proportionally increasing complexity, as the same controller hardware and software framework manage both DRAM and NVM operations.
Data Source
AI summary
Systems and methods are provided for supporting use of non-volatile memory (NVM) on a double data rate (DDR) memory channel for an information handling system so that non-volatile memory devices (e.g., such as Phase Change Memory “PCM” devices) may be employed for main memory usage. In one possible implementation, information handling system memory reads may be managed directly in hardware as memory semantics via use code, while memory writes may be separately handled, e.g., via an operating system (OS)/driver. In another possible implementation, both DRAM-based and NVM-based memory systems may be populated for an information handling system.