NVM Die On-Chip Data Augmentation for ML Training
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Solution Overview
Problem
Current machine learning systems face challenges in efficiently augmenting data for training, particularly in deep learning applications, as they often require large datasets and may suffer from overfitting due to limited initial data, which can be addressed by implementing data augmentation within non-volatile memory (NVM) dies to generate varied training data without transferring large amounts of data.
Innovation Solution
Incorporating data augmentation controllers and circuits within NVM dies to perform data augmentation operations such as noise addition, skewing, cropping, and rotation of training data, thereby generating augmented data sets directly within the memory, reducing the need for extensive data transfer and leveraging inherent noise features for improved training efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data augmentation is performed externally to generate varied training data, then the training data diversity is improved, but the data transfer volume and processing time increase
Solution Approach 1:
The patent merges the data augmentation functionality with the NVM die by integrating data augmentation controllers and circuits directly into the memory device. This combination allows the NVM die to perform data augmentation operations internally, eliminating the need to transfer large volumes of data between external systems and reducing processing time while maintaining training data diversity.
Solution Approach 2:
The NVM die is configured to perform data augmentation operations autonomously using its own integrated circuits and controllers. The die serves itself by generating varied training data internally through operations such as noise addition, skewing, cropping, and rotation, without requiring external processing systems, thereby minimizing data transfer and leveraging inherent noise features for improved training efficiency.
2Adaptability or versatility
If data augmentation operations are performed externally, then the training data variety is improved, but the processing time and computational resources increase
Solution Approach 1:
The patent merges data augmentation functionality with the NVM die by integrating data augmentation controllers and circuits directly into the memory device. This combination allows the NVM die to perform data augmentation operations internally, eliminating the need to transfer large volumes of data between external systems and reducing processing time while maintaining training data diversity.
Solution Approach 2:
The data augmentation operations are performed preliminarily within the NVM die before data is transferred to processing systems. By pre-generating augmented data sets internally, the system reduces the time required for external processing and minimizes the computational resources needed at the processing stage, as the data is already prepared in varied forms.
3Productivity
If on-chip data augmentation is implemented, then the training efficiency is improved, but the device complexity increases
Solution Approach 1:
The patent merges the data augmentation functionality with the NVM die by integrating data augmentation controllers and circuits directly into the memory device. This combination allows the NVM die to perform data augmentation operations internally, eliminating the need to transfer large volumes of data between external systems and reducing processing time while maintaining training data diversity.
Solution Approach 2:
The NVM die is designed with multi-functionality, serving both as a storage device and a data augmentation processor. The integrated data augmentation controllers and circuits enable the die to perform multiple functions including data storage, data augmentation operations (noise addition, skewing, cropping, rotation), and training data generation, thereby improving training efficiency without requiring separate dedicated hardware for each function.
Data Source
AI summary
Methods and apparatus are disclosed for implementing machine learning data augmentation within the die of a non-volatile memory (NVM) apparatus using on-chip circuit components formed on or within the die. Some particular aspects relate to configuring under-the-array or next-to-the-array components of the die to generate augmented versions of images for use in training a Deep Learning Accelerator of an image recognition system by rotating, translating, skewing, cropping, etc., a set of initial training images obtained from a host device. Other aspects relate to configuring under-the-array or next-to-the-array components of the die to generate noise-augmented images by, for example, storing and then reading training images from worn regions of a NAND array to inject noise into the images.