Non-Volatile Memory Address Management via Digest Extraction
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Solution Overview
Problem
Quad-level cell (QLC) memory systems face challenges in fast data initialization due to complex encoding schemes and increased bit error rates, leading to prolonged header scan times and performance imbalances across multi-level pages.
Innovation Solution
The solution involves allocating data to multi-level pages with varying data integrity levels, using a digest to store address information on the page with the lowest bit error rate, and adjusting the error correction coding rate to optimize data storage and retrieval efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC memory cells with complex encoding schemes are used to increase storage capacity, then storage density is improved, but header scan time and initialization latency increase significantly
Solution Approach 1:
The page is divided into multiple multi-level pages (first multi-level page, second multi-level page, third multi-level page, fourth multi-level page), each storing data for different encoding schemes. This segmentation allows the system to optimize header storage separately for each encoding type, reducing overall header scan time during initialization.
Solution Approach 2:
Address information (headers) for the second, third, and fourth multi-level pages is extracted and stored in a digest on the first multi-level page. This extraction eliminates the need to scan separate headers for these pages during initialization, significantly reducing header scan time while maintaining the high storage density of QLC cells.
2Quantity of substance
If more memory states are read to ascertain cell memory state for higher storage capacity, then storage capacity per cell is improved, but bit error rate increases
Solution Approach 1:
Different error correction codes are applied to different multi-level pages based on their specific encoding schemes and error characteristics. The first multi-level page uses one error correction code while the second, third, and fourth pages use another error correction code. This local quality approach optimizes error correction efficiency for each page's specific error profile, improving overall reliability.
Solution Approach 2:
The system changes error correction parameters by applying different error correction codes to different multi-level pages. This parameter adaptation allows the system to optimize the balance between storage capacity and error rate for each specific encoding scheme used in the QLC memory cells.
3Reliability
If redundancy data is increased to improve error correction capability, then data reliability is improved, but storage efficiency and write capacity decrease
Solution Approach 1:
Different error correction codes with different redundancy levels are applied to different multi-level pages based on their specific needs. This local quality approach ensures that each page receives the appropriate level of error correction protection, optimizing the balance between reliability and storage efficiency for the entire page structure.
Data Source
AI summary
A method, an apparatus, and a system for data address management in non-volatile memory. Write data is allocated to each of a plurality of multi-level pages configured for storage on a page of a non-volatile memory array. A digest is associated with the write data of one multi-level page based on an attribute for that multi-level page. This attribute differs from the attributes of at least one of the other multi-level pages. An amount of redundancy data to be stored with write data on the multi-level page is reduced to account for the associated digest. A digest may be distributed among a plurality of ECC codewords of a multi-level page. The reduced redundancy data, the digest, and the write data for the multi-level page are stored on the page along with the write data for each of the other multi-level pages of the plurality of multi-level pages.