3D NVM DRAM Integration with Isolation Devices
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Solution Overview
Problem
Current system architectures that utilize both volatile and non-volatile memory devices separately consume large area and reduce data transfer speed between static random-access memory (SRAM) and non-volatile memory (NVM).
Innovation Solution
A three-dimensional (3D) non-volatile memory (NVM) structure combination with dynamic random access memory (DRAM) is introduced, where DRAM and NVM arrays are arranged with isolation devices to control bit line connections, enabling efficient data transfer and reducing power consumption by optimizing layout and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If volatile memory (SRAM/DRAM) and non-volatile memory (NVM) are implemented as separate devices in current system architectures, then each memory type can be optimized independently, but large area is consumed and data transfer speed between SRAM and NVM is reduced
Solution Approach 1:
The patent merges volatile DRAM and non-volatile NVM into a single integrated memory device structure. The DRAM array and NVM array are combined in one device with shared bit lines and word lines, eliminating the need for separate memory devices. This integration reduces the overall system area while maintaining the ability to independently optimize each memory type's performance characteristics through dedicated circuitry and control mechanisms.
2Ease of manufacture
If volatile memory (SRAM/DRAM) and non-volatile memory (NVM) are implemented as separate devices, then each memory type can be optimized independently, but data transfer speed between SRAM and NVM is reduced
Solution Approach 1:
The patent introduces shared bit lines and word lines as intermediary structures that enable direct communication between the DRAM array and NVM array within the same device. These shared conductors act as mediators that facilitate high-speed data transfer between the two memory types without requiring external interconnects, thereby improving data transfer speed while maintaining independent optimization capabilities through dedicated sense amplifiers and control logic.
3Area of stationary object
If DRAM and NVM arrays are integrated in a 3D structure with shared bit lines, then layout area is reduced and data transfer speed is improved, but device complexity increases due to isolation devices and control mechanisms
Solution Approach 1:
The patent transitions from a planar 2D layout to a three-dimensional stacked architecture where the DRAM array and NVM array are positioned in different vertical layers. This dimensional change allows both memory arrays to share the same footprint area while maintaining physical separation through isolation devices. The 3D structure reduces layout area by utilizing vertical space, and the isolation devices manage the increased complexity by providing clear electrical separation between layers, simplifying the control mechanisms needed for independent operation.
4Area of stationary object
If DRAM and NVM arrays are integrated in a 3D structure with shared bit lines, then layout area is reduced, but device complexity increases due to isolation devices and control mechanisms
Solution Approach 1:
The patent implements a nested structure where the NVM array is positioned beneath the DRAM array in a vertical stacking configuration. The isolation devices are integrated at the interfaces between layers, nesting the separation functionality within the overall device structure. This nesting approach reduces the layout area by maximizing space utilization in the vertical dimension while minimizing the complexity of isolation devices by locating them only at necessary interface points rather than throughout the entire structure.
Data Source
AI summary
Technologies for a three-dimensional (3D) multi-bit non-volatile dynamic random access memory (nvDRAM) device, which may include a DRAM array having a plurality of DRAM cells with single or dual transistor implementation and a non-volatile memory (NVM) array having a plurality of NVM cells with single or dual transistor implementations, where the DRAM array and the NVM array are arranged by rows of word lines and columns of bit lines. The nvDRAM device may also include one or more of isolation devices coupled between the DRAM array and the NVM array and configured to control connection between the dynamic random access bit lines (BLs) and the non-volatile BLs. The word lines run horizontally and may enable to select one word of memory data, whereas bit lines run vertically and may be connected to storage cells of different memory address.