Non-Volatile Memory Drift Detection via Bit Flipping

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Solution Overview

Problem

Non-volatile memory devices face challenges in detecting drift in memory cells, which can lead to incorrect data reading and increased latency due to the need for higher read voltages after a certain time, potentially causing data corruption and requiring time-consuming error correction decoding.

Innovation Solution

The implementation of a technique where bits are encoded with more set values than reset values, allowing for detection of drift by reading the bits with a lower safe demarcation voltage and re-reading with a higher unsafe demarcation voltage if drift is detected, thereby reducing read latency and identifying silent data corruption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a higher read voltage is used to read data from non-volatile memory cells after drift occurs, then data can be read, but read latency increases and the risk of writing 1s to 0 values increases

Engineering Contradiction:
Improvedata reading accuracyVSAvoidread latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary actions by encoding bits with more set values than reset values and using error correction codes to detect drift before it causes data corruption. This allows the system to prepare detection mechanisms in advance, enabling early identification of drift conditions without immediately resorting to higher read voltages, thus reducing latency while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by continuously monitoring read errors and using error correction decoding to detect drift conditions. When drift is detected through feedback from error patterns, the system can switch to higher read voltages only when necessary, optimizing the balance between read speed and data integrity.

Inventive Principle:
Principle #23Feedback

2Reliability

If error correction decoding is performed to correct drift-related errors, then data integrity is maintained, but read latency increases due to time-consuming decoding operations

Engineering Contradiction:
Improvedata integrityVSAvoiddecoding time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system applies partial action by using error correction codes that provide sufficient protection for drift detection without requiring full decoding operations for every read. The error correction mechanism is designed to handle the specific error patterns caused by drift, allowing the system to correct errors efficiently without performing excessive decoding that would increase latency.

Inventive Principle:
Principle #16Partial or excessive action

3Difficulty of detecting and measuring

If bits are encoded with more set values than reset values, then drift detection becomes easier, but the complexity of the encoding scheme increases

Engineering Contradiction:
Improvedrift detection easeVSAvoidencoding scheme complexity
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The system changes the parameter of bit encoding by using a specific encoding scheme where bits are encoded with more set values than reset values. This parameter change makes drift detection easier because drift manifests as a measurable imbalance in the encoded bit patterns, while the encoding scheme itself remains a standard extension of existing bit encoding methods.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10481974B2Apparatus, non-volatile memory storage device and method for detecting drift in non-volatile memory
Publication Date: 2019.11.19 SK HYNIX NAND PRODUCT SOLUTIONS CORP
  • US10481974B2 patent drawing
  • US10481974B2 patent drawing
  • US10481974B2 patent drawing

AI summary

Provided are an apparatus, non-volatile memory storage device and method for detecting drift in in non-volatile memory. A determination is made as to whether bits to write have more of a first value than a second value. Each of the bits are flipped to another of the first or second value when the bits have more of the first value than the second value. Indication is made whether the bits were flipped or not flipped. Parity is calculated for the bits and the bits and the parity for the bits are written to a location in the non-volatile memory. The bits at the location in the non-volatile memory are read and each of the bits having the first value are flipped to the second value and each of the bits having the second value are flipped to the first value in response to indication that the bits were flipped.