Nonvolatile Memory Data Integrity Check via Dual-Level Programming
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Solution Overview
Problem
In data processing systems, initial power-up or reset operations on nonvolatile memory (NVM) are error-prone due to the 'dirty' state of operation parameters, leading to potential destructive system failures, as reference voltages are not yet accurate and trims are not set, causing incorrect read operations.
Innovation Solution
The execute control code and reference data are divided into two parts, programmed with the same data but using different programming levels: production data at a production program verify (PPV) level and margin data at a reduced margin program verify (MPV) level, with comparisons between them used to detect compromised data, and an additional status bit tracks comparison failures to initiate refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the NVM is read during initial power-up or reset operations, then the system can execute commands, but the read operations are error-prone due to dirty state operation parameters causing incorrect values
Solution Approach 1:
The patent divides the stored data into two separate sections: production data and margin data. Both sections contain the same execute control code and reference data, but are programmed at different verify levels. This segmentation allows the system to compare the two sections to detect errors, resolving the contradiction between maintaining data accuracy and avoiding increased complexity.
Solution Approach 2:
The patent creates a copy of the production data in the margin data section. This copy is programmed at a reduced margin program verify level, allowing it to serve as a reference for detecting errors in the production data. The copying approach enables error detection without requiring complex additional hardware or procedures.
2Reliability
If the production data is programmed at a higher verify level, then the data integrity is improved, but the read operations during initial power-up remain error-prone due to inaccurate reference voltages
Solution Approach 1:
The patent performs a preliminary comparison between production data and margin data during initial power-up or reset operations, before the reference voltages have stabilized. By comparing the two sections of data, the system can detect errors that occur during this dirty state period, allowing for corrective action before executing critical commands.
Solution Approach 2:
The patent implements a feedback mechanism where the margin data serves as a reference to verify the integrity of the production data. When a mismatch is detected between the two sections, the system can identify the error and take corrective action, such as preventing execution of the affected commands or initiating a refresh operation.
3Reliability
If the system performs error detection comparisons between production data and margin data, then data integrity is maintained, but additional time is required for comparison operations
Solution Approach 1:
The patent applies error detection selectively rather than continuously. The comparison between production data and margin data is performed specifically during initial power-up or reset operations when the risk of errors is highest. This partial application of error detection maintains data integrity during critical periods without imposing continuous time overhead during normal operations.
Data Source
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AI summary
A memory system includes a memory array, control circuitry, and comparator circuitry. The memory array includes a first section having a first plurality of programmed bitcells having a first threshold voltage distribution and a second section having a second plurality of programmed bitcells having a second threshold voltage distribution which has a lower average threshold voltage than the first threshold voltage distribution. The first plurality and second plurality of programmed bitcells are programmed with a same set of data values. The control circuitry is configured to provide a read request to the memory array and receive read data in response to the read request, wherein the read data comprises first read data from the first section and second read data from the second section. The comparator circuitry is configured to compare the first read data to the second read data and generate an error indicator in response to the compare.