Fault Tolerant Non Volatile Memory Dual Threshold Detection
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Solution Overview
Problem
Non-volatile memory (NVM) devices often suffer from 'tail bits' that fail during use, leading to data retention issues, which are not adequately addressed during production testing, resulting in increased power consumption and cost due to the need for fault tolerance solutions like redundant bit storage or error correction coding.
Innovation Solution
A fault-tolerant NVM system that detects and corrects errors separately, using a single parity bit for each set of NVM bits, reducing area, complexity, and cost by identifying 'bad' bits through characteristic attribute shifts and employing dual threshold sense amplifiers to distinguish between good and bad bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant bit storage or error correction coding is used to address tail bits, then reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent changes the detection parameter from traditional single-threshold reading to dual-threshold reading. By reading the same memory cell with two different threshold voltages and comparing the results, the system can detect tail bit failures without requiring redundant storage or complex ECC circuits. This parameter change enables fault detection using existing memory structure, avoiding the complexity increase associated with traditional fault tolerance methods.
2Reliability
If redundant bit storage or error correction coding is used to address tail bits, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent uses dual-threshold voltage parameter changes to detect faults in existing memory bits rather than activating additional redundant bits or ECC circuits. This approach detects tail bit failures using the same memory structure with modified reading parameters, significantly reducing the additional power consumption that would result from continuously monitoring or correcting redundant storage elements.
3Device complexity
If traditional single threshold reading is used, then device complexity is minimized, but manufacturing precision is insufficient to detect tail bits
Solution Approach 1:
The patent introduces dual-threshold voltage parameters for reading memory cells. By comparing results from two different threshold readings, the system can identify tail bit failures that would be indistinguishable from valid data in single-threshold systems. This parameter enhancement improves detection precision without significantly increasing device complexity, as it uses the existing memory structure with modified reading operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient error correction with reduced resources, as 'bad' bits are identified and corrected using parity logic, minimizing the need for extensive error correction codes, thereby reducing the size and power consumption of memory circuits.
Implementation Method 1
dual threshold sense amplifiers to distinguish between good and bad bits
Data Source
AI summary
Methods and structure for fault tolerant Non Volatile Memory (NVM) devices are provided. Readings of selected memory cells are compared to two thresholds above and below a neutral value. Consistency of comparison outputs is used to determine a good or bad reading. Parity bit correction can be used to correct bad readings.