NVM Dummy Rows for Memory Operation Support
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Solution Overview
Problem
Conventional Non-Volatile Memory (NVM) systems face challenges in efficiently supporting memory operations due to the limitations in configuring bit lines and source lines for accurate read and programming operations, particularly in integrating dummy rows to enhance memory array functionality.
Innovation Solution
The implementation of a memory array with dummy rows and columns, where dummy cells are strategically connected to bit lines and source lines to enable selective actuation for read and programming operations, allowing for the application of reference voltages and programming voltages to memory cells, thereby facilitating accurate data retrieval and programming without interfering with column decoding signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dummy rows are added to the memory array to support memory operations, then the ability to perform read and programming operations is improved, but the device complexity increases
Solution Approach 1:
The dummy rows are configured with dual connectivity: they connect to bit lines for reading operations and to source lines for programming operations. This multi-functional design allows the same dummy row structure to support both read and programming operations, resolving the contradiction by making the added structure serve multiple purposes rather than being dedicated to a single function.
Solution Approach 2:
The memory array is segmented into functional portions (dummy rows) and non-functional portions (actual memory cells). The dummy rows are strategically positioned and connected to specific bit line groups and source line groups, allowing independent control and activation. This segmentation enables the system to activate only the necessary portions for each operation type, managing complexity through modular organization.
2Manufacturing precision
If dummy cells are connected to both bit lines and source lines, then the accuracy of voltage application is improved, but the difficulty of controlling column decoding signals increases
Solution Approach 1:
The control system dynamically configures the connectivity of dummy cells based on the operation being performed. During read operations, dummy cells are connected to bit lines through column decoders. During programming operations, dummy cells are connected to source lines. This dynamic reconfiguration allows the same physical structure to serve different functions with high precision while maintaining control through operational context awareness.
Solution Approach 2:
The control circuit is designed to pre-establish the appropriate connections for the intended operation before actual data processing begins. The system determines whether a read or programming operation is required and proactively configures the dummy row connections accordingly, ensuring that the correct voltage paths are established before the operation commences, thereby avoiding interference with column decoding signals.
3Measurement precision
If multiple bit line groups are used for read operations, then the read accuracy is improved, but the time required for operation increases
Solution Approach 1:
The bit lines are segmented into multiple groups, with each group connected to specific dummy row portions. This segmentation allows parallel processing of different bit line groups during read operations. By dividing the bit line infrastructure into independent, concurrently operable groups, the system achieves higher read accuracy through dedicated reference voltage application to each group while maintaining efficient operation times through parallel execution.
Data Source
AI summary
A memory array includes rows and columns with memory cell portion and a dummy cell portion. Bit lines are connected to the memory cells and to the dummy cell portion. The dummy cell portion includes a first row of dummy cells and a second row of dummy cells. The dummy cells in the first row have a first connection to a corresponding bit line of a first bit line group of the bit lines and a second connection to a first source line. The dummy cells in the second row have a first connection to a corresponding bit line of a second bit line group of the plurality of bit lines and a second connection to a second source line. The dummy cells are selectively actuated to couple voltages at the first and second source lines to the first and second bit line groups, respectively, depending on memory operating mode.