Non-Volatile Memory Programming via Dynamic Pass Voltage Control
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Solution Overview
Problem
Existing memory devices face challenges in improving data input/output speed, particularly during programming operations in non-volatile memory devices, due to higher error rates and cell-to-cell interference, which complicates the storage of multi-bit data.
Innovation Solution
The implementation of an Incremental Step Pulse Programming (ISPP) method that dynamically adjusts the pass voltage level and program mode based on verification results, applying multiple program pulses to non-volatile memory cells while controlling the bit line potential, thereby reducing error rates and speeding up programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple program pulses are applied to non-volatile memory cells to store multi-bit data, then data storage capacity is improved, but error rates increase due to cell-to-cell interference
Solution Approach 1:
The patent segments the programming operation into multiple discrete program pulses with incremental voltage steps. Each pulse programs a portion of the multi-bit data, allowing verification between pulses to detect and correct errors before completing the full programming sequence. This segmentation enables reliable multi-bit storage by breaking down the complex programming task into manageable stages.
Solution Approach 2:
The patent implements verification operations between program pulses to monitor programming status and detect errors. Based on verification results, the system adjusts subsequent programming parameters such as pulse voltage levels and timing. This feedback mechanism enables real-time error detection and correction, maintaining high reliability while storing multi-bit data.
2Productivity
If pass voltage level is increased to speed up programming operations, then programming speed is improved, but cell-to-cell interference increases causing higher error rates
Solution Approach 1:
The patent dynamically adjusts the pass voltage level based on the programming stage and verification results. Instead of using a fixed high voltage that causes interference, the system adapts the voltage magnitude to match the actual programming needs at each pulse, speeding up operations while maintaining reliability through controlled voltage progression.
Solution Approach 2:
The patent changes multiple parameters including pass voltage level, program pulse width, and timing intervals based on verification outcomes. These parameter adjustments optimize the balance between programming speed and error rate by fine-tuning the electrical characteristics during the programming sequence.
3Reliability
If verification operations are performed frequently to reduce error rates, then data accuracy is improved, but time spent on programming operations increases
Solution Approach 1:
The patent performs verification operations selectively at critical points during the programming sequence rather than after every single pulse. This partial verification approach maintains data accuracy by checking at key stages while avoiding the time penalty of continuous verification, optimizing the balance between reliability and speed.
4Productivity
If bit line discharge time is reduced to improve programming speed, then productivity is improved, but threshold voltage distribution widens reducing storage accuracy
Solution Approach 1:
The patent performs preliminary discharge of bit lines and channels before applying program pulses to ensure they are fully reset. This preliminary action prevents residual charges from affecting the threshold voltage distribution, allowing fast programming operations while maintaining narrow voltage distributions and high storage accuracy.
Data Source
AI summary
A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.