Non-Volatile Memory Error Correction Yield
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Solution Overview
Problem
Non-volatile memory (NVM) devices face high production defects, leading to low yields and increased costs due to defective memory cells, bit and word lines, and sense amplifiers, which existing redundant element designs fail to effectively address when defect numbers are high.
Innovation Solution
Implementing a system with forward error correction (FEC) and cyclic redundancy check (CRC) operations in NVM arrays to correct and detect errors, allowing substitution with redundant elements and partitioning the array into classes with specified FEC operations and priorities for error correction, ensuring robustness against defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If redundant elements are utilized in NVM design to replace defective elements, then production yield is improved, but the solution becomes ineffective when the number of defects is very high
Solution Approach 1:
The patent changes the parameter of error correction capability from basic redundancy to advanced FEC (Forward Error Correction) and CRC (Cyclic Redundancy Check) operations. This allows the system to correct a higher number of defects by implementing multi-bit error correction algorithms that can handle scenarios where traditional redundancy fails.
Solution Approach 2:
The patent combines multiple error correction mechanisms (FEC and CRC) into a composite error correction system. This composite approach integrates different correction strategies to handle various defect scenarios, making the system more robust against high numbers of defects while maintaining improved production yield.
2Reliability
If FEC and CRC operations are implemented in NVM arrays, then error correction and detection capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the NVM array into multiple classes or groups, applying FEC and CRC operations to specific segments rather than the entire array. This segmentation reduces the computational complexity and resource requirements while maintaining effective error correction capability for the most critical portions of the memory.
Solution Approach 2:
The patent applies different levels of error correction (FEC and CRC) to different regions or classes of the NVM array based on their specific requirements. This local quality approach ensures that resources are allocated efficiently, providing enhanced protection where needed while reducing complexity in less critical areas.
3Productivity
If NVM array is partitioned into classes with specified FEC operations and priorities, then error correction efficiency is improved, but device complexity increases
Solution Approach 1:
The patent partitions the NVM array into multiple classes with different FEC operation priorities, allowing efficient error correction by processing critical classes first. This segmentation enables the system to focus computational resources on the most important data regions, improving overall error correction efficiency while managing complexity through structured organization.
Solution Approach 2:
The patent performs preliminary classification of NVM array elements into different classes based on their error correction requirements and priorities. This preliminary action allows the system to pre-determine the most efficient correction strategy, reducing the complexity of real-time decision-making during error correction operations.
Data Source
AI summary
A method and system for a non-volatile memory (NVM) with multiple bits error correction are provided and may include detecting bit errors in a memory element, of a NVM array integrated within a chip, which remain uncorrected after forward error correction. A redundant memory element may be utilized when the errors may be detected utilizing a cyclic redundancy check, may be within the NVM array, and may include secure information. Access to the secure information and/or the chip may be disabled when the errors are detected. The FEC operation may include one or both of an error location operation and a correction operation. The errors may be corrected when a location may be known to include the errors. The NVM array may be partitioned into regions. At least one of the redundant memory elements may be substituted in place of the memory element based on a substitution priority.