Front and Back Gate NVM Structure for Threshold Voltage Variation
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Solution Overview
Problem
Conventional memory cell implementations using floating gates face challenges in efficiently storing and detecting logic states due to limited variation in threshold voltage, which affects read operations and energy consumption in mobile devices.
Innovation Solution
The implementation of a memory cell with both front and back gates, where the back gate is a floating gate used to store charge, allowing for a greater variation in threshold voltage and improved logic state detection, and a non-insulative region coupled to a word line for efficient programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional floating gate memory cells are used, then the structure is simple, but the threshold voltage variation is limited affecting read operations
Solution Approach 1:
The memory cell is segmented into two separate gates: a front gate for conventional control and a back gate for additional threshold voltage modulation. This segmentation allows independent optimization of each gate's function, enabling greater overall threshold voltage variation while maintaining a relatively simple integrated structure.
Solution Approach 2:
The invention adds a vertical dimension to the gate structure by introducing a back gate beneath the channel, in addition to the conventional front gate. This dimensional expansion from single-sided to dual-sided gate control enables significantly increased threshold voltage variation without planar complexity.
2Ease of manufacture
If conventional floating gate memory cells are used, then the manufacturing process is simple, but energy consumption is high in mobile devices
Solution Approach 1:
The fabrication process is segmented into standard front-gate formation steps followed by separate back-gate formation steps. This segmentation allows utilization of existing CMOS manufacturing capabilities while adding the back gate through established processes like well implantation or thin film deposition, maintaining ease of manufacture.
Solution Approach 2:
The invention changes the electrical parameters of the memory cell by introducing a second gate that provides additional control over the channel. This enables lower operating voltages and reduced programming currents, thereby decreasing energy consumption without complicating the fundamental fabrication approach.
3Device complexity
If conventional floating gate memory cells are used, then the structure is simple, but threshold voltage variation is limited
Solution Approach 1:
The control function is segmented between front and back gates, with the back gate specifically dedicated to threshold voltage modulation. This segmentation enables the back gate to provide substantial additional voltage variation (exceeding 1V) independent of the front gate, significantly enhancing reliability.
Solution Approach 2:
By adding the back gate in the vertical dimension beneath the channel, the invention creates a dual-gate FET structure that provides enhanced control over carrier flow. This dimensional addition enables greater threshold voltage variation range, improving memory window and read reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the detection of logic states during read operations and reduces energy consumption by increasing the variation in threshold voltage, improving the performance and efficiency of memory cells in mobile devices.
Implementation Method 1
a floating back gate region, a first portion of the floating back gate region being below the second semiconductor region
Implementation Method 2
applying the voltage signal to a non-insulative region of the memory cell to transfer charge to a floating back gate region of the memory cell
Data Source
AI summary
Certain aspects of the present disclosure are directed to a memory cell implemented using front and back gate regions. One example memory cell generally includes a first semiconductor region, a second semiconductor region, and a third semiconductor region, the second semiconductor region being disposed between the first semiconductor region and the third semiconductor region. The memory cell may also include a front gate region disposed above the second semiconductor region, a floating back gate region, a first portion of the floating back gate region being disposed below the second semiconductor region, and a non-insulative region disposed adjacent to the floating back gate region.