NVM Erase Gate and Logic Gate CMP Layout for Lower Topography
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing topography variations and suppressing the increase in lithography operations due to height differences between non-volatile memory (NVM) cells and peripheral logic circuits during the manufacturing process of semiconductor devices.
Innovation Solution
A method involving the formation of stack structures with specific dielectric and conductive layers, followed by chemical-mechanical polishing (CMP) and patterning to create erase gates and logic gates, which helps in reducing the height difference and improving the etching process, while also using dummy gate structures to minimize the loading effect during CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate formation processes are used for NVM cell stacks and logic circuit gates, then each structure can be optimized independently, but topography variations and height differences increase
Solution Approach 1:
The patent merges the formation processes of NVM cell stacks and logic circuit gates into a single unified process. Dummy gate structures are formed simultaneously with logic gates using the same patterning and deposition steps, eliminating separate formation processes. This unified approach reduces topography variations while maintaining the ability to optimize both structure types through controlled material deposition and removal.
Solution Approach 2:
The patent introduces dummy gate structures as intermediary elements that serve multiple functions: they act as placeholders during NVM stack formation, enable unified processing, and are later replaced with actual logic gates. These dummy gates mediate between the conflicting requirements of simultaneous formation and structure-specific optimization, allowing the process to achieve both goals.
2Shape
If unified formation process is used for NVM cell stacks and logic circuit gates, then topography variations are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct phases: first forming NVM stacks and dummy gates together, then removing dummy gates in specific regions, and finally forming logic gates in those regions. This segmentation transforms a complex unified process into manageable stages, each with clear objectives and controlled outcomes, reducing overall process complexity.
Solution Approach 2:
The patent performs preliminary actions by forming dummy gate structures in advance before final logic gate formation. These dummy gates are created during the NVM stack formation process, enabling subsequent selective removal and replacement with actual logic gates. This preliminary action simplifies the overall process by preparing the structure beforehand rather than requiring complex real-time adjustments.
3Manufacturing precision
If dummy gate structures are formed, then loading effect during CMP is minimized, but additional patterning steps are required
Solution Approach 1:
The patent makes the dummy gate structures multi-functional: they serve as loading elements during CMP to ensure uniform polishing across the wafer, act as temporary placeholders during NVM stack formation, and are later replaced with logic gates. This universality allows a single structure to fulfill multiple process requirements, reducing the need for additional dedicated lithography steps.
Solution Approach 2:
The patent employs a discard-and-recover strategy with dummy gate structures: dummy gates are formed and used during CMP and NVM stack formation, then selectively removed in logic circuit regions, and finally replaced with actual logic gates. This approach allows the dummy gates to serve their temporary purpose and then be discarded, with their location and structure recovered as the basis for final logic gate formation, minimizing additional lithography operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturing process by reducing topography variations and improving the performance of further etching processes, thereby addressing the challenges of height differences and increasing lithography operations.
Implementation Method 1
performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures
Data Source
AI summary
Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.