Gate-Last NVM Logic Integration via Nanocrystal Extraction
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Solution Overview
Problem
The integration of non-volatile memories (NVMs) with logic transistors is challenging due to different requirements for charge storage, particularly with unique layers like floating gates, nanocrystals, or nitride, which complicate their co-integration.
Innovation Solution
A method is developed where the gate structure of NVM cells is formed with a charge storage layer while masking the logic region, using a hard mask to create sidewall spacers, and simultaneous source/drain implants are performed in both regions, allowing for the integration of NVM and logic transistors with high-k gate dielectrics and metal gates using a gate-last methodology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If floating gates or nanocrystals are used for charge storage in NVM transistors, then charge storage capability is improved, but integration with logic transistors becomes difficult due to unique layer requirements
Solution Approach 1:
The patent extracts the charge storage function from the traditional floating gate structure and implements it using nanocrystals formed within the gate dielectric layer. This allows the charge storage mechanism to be integrated within the logic transistor gate structure itself, eliminating the need for separate floating gate layers and enabling co-integration of NVM and logic transistors using the same high-k gate dielectric process
Solution Approach 2:
The high-k gate dielectric layer serves multiple functions: it acts as the gate insulator for logic transistors and simultaneously provides the matrix in which nanocrystals are formed for charge storage in NVM transistors. This multi-functional approach allows both logic and memory devices to share the same gate dielectric process, simplifying integration
2Reliability
If different charge storage layers are used for NVM transistors, then charge storage is enabled, but manufacturing process options are limited
Solution Approach 1:
The patent changes the material parameter of the gate dielectric from traditional silicon oxide to high-k dielectric materials, and changes the charge storage mechanism from floating gate to nanocrystals. These parameter changes enable compatibility with existing high-k gate dielectric manufacturing processes while providing reliable charge storage functionality
3Speed
If gate-last methodology is used with high-k gate dielectrics and metal gates, then logic transistor performance is improved, but NVM integration becomes more challenging
Solution Approach 1:
The patent performs preliminary actions by forming the nanocrystals within the high-k gate dielectric layer before the gate-last processing steps. This preliminary formation of the charge storage structure allows subsequent metal gate deposition and patterning to proceed without affecting the NVM functionality, enabling both logic performance improvement and NVM integration
Data Source
AI summary
A method of making a semiconductor structure uses a substrate and includes a logic device in a logic region and a non-volatile memory (NVM) device in an NVM region. An NVM structure is formed in the NVM region. The NVM structure includes a control gate structure and a select gate structure. A protective layer is formed over the NVM structure. A gate dielectric layer is formed over the substrate in the logic region. The gate dielectric layer includes a high-k dielectric. A sacrificial gate is formed over the gate dielectric layer in the logic region. A first dielectric layer is formed around the sacrificial gate. Chemical mechanical polishing is performed on the NVM region and the logic region after forming the first dielectric layer. The sacrificial gate is replaced with a metal gate structure.