Non-Volatile Memory Gate Structure Simplification
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Solution Overview
Problem
Non-volatile memory integration into general CMOS logic processes is complicated due to issues with controlling the thickness of the top oxide layer, increased manufacturing costs, and alignment errors between gates, leading to complex manufacturing processes and reduced efficiency.
Innovation Solution
A non-volatile memory design featuring a substrate with doped regions and gate structures comprising a tunneling dielectric layer and charge trapping structure, utilizing channel-hot-hole-induced hot-electron injection for programming and erasing, which simplifies integration and reduces manufacturing costs by eliminating the need for precise top oxide layer control and dual polysilicon layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a two-layer gate structure (ONO) is used in non-volatile memory, then charge trapping capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the top oxide layer (ONO structure) from the gate stack, retaining only the nitride charge trapping layer. This simplifies the gate structure from two layers to one layer, reducing manufacturing complexity while preserving charge trapping capability through the retained nitride layer.
Solution Approach 2:
The single nitride layer performs multiple functions: it serves as both the charge trapping layer and the gate dielectric, eliminating the need for separate oxide layers. This multi-functional design simplifies the overall structure while maintaining the necessary electrical characteristics for memory operation.
2Ease of manufacture
If hydrofluoric acid is used for etching the top oxide layer, then oxide removal is achieved, but thickness control becomes difficult
Solution Approach 1:
The patent removes the top oxide layer entirely from the gate structure, eliminating the need for hydrofluoric acid etching processes. By extracting this problematic layer, the manufacturing process avoids the thickness control issues associated with HF etching while still achieving the necessary gate structure characteristics.
3Adaptability or versatility
If select transistor is extended onto memory transistor, then device integration is achieved, but alignment precision requirements increase
Solution Approach 1:
The patent segments the transistor gates into distinct, non-overlapping regions. The select transistor gate and memory transistor gate are separated and do not require precise alignment with each other, eliminating the alignment errors that would occur if one transistor extended onto the other. This segmentation maintains device integration while reducing alignment precision requirements.
4Reliability
If dual polysilicon layers are used for gate structures, then memory functionality is achieved, but manufacturing cost increases
Solution Approach 1:
The patent extracts and eliminates one of the dual polysilicon layers, retaining only the necessary nitride-based gate structure. This reduction from two polysilicon layers to a single simplified gate structure decreases material costs and processing steps while maintaining the essential memory functionality through the preserved charge trapping capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the efficiency and reliability of memory operations by improving write and erase speeds, reducing current leakage, and increasing charge retention, while simplifying the manufacturing process and reducing costs.
Implementation Method 1
a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up
Implementation Method 2
a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up
Implementation Method 3
the channel hot holes are used to induce the hot electron injection
Implementation Method 4
a first doped region, a second doped region, a third doped region... the first, second, and third doped regions may be p-doped regions, and the substrate may be an n-substrate
Data Source
AI summary
A non-volatile memory including a substrate, a first doped region, a second doped region, a third doped region, a first gate structure, and a second gate structure is disclosed. The doped regions are disposed in the substrate and the second doped region is disposed between the first doped region and the third doped region. The first gate structure is disposed on the substrate between the first doped region and the second doped region. The second gate structure is disposed on the substrate between the second doped region and the third doped region, and comprises a tunneling dielectric layer, a charge trapping structure and a gate from the bottom up.