Non-Volatile Memory Gate Pattern Simplification
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Solution Overview
Problem
The existing methods for fabricating non-volatile memory devices are complicated, leading to limitations in integration density, signal delay, and performance deterioration due to the need for forming a charge blocking layer contact hole, which results in unstable interfaces and voids that can cause short circuits.
Innovation Solution
A method that omits the contact process between the floating gate and control gate electrodes by removing the control gate and charge blocking layers in the peripheral circuit region, thereby simplifying the fabrication process and reducing the height of the gate pattern to prevent void generation and improve integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge blocking layer contact hole is formed to connect floating gate electrode and control gate electrode in peripheral circuit region, then the transistors can operate as normal transistors, but the fabrication process becomes complicated and integration density is limited
Solution Approach 1:
The patent extracts and removes the charge blocking layer and control gate electrode from the peripheral circuit region, eliminating the need to form charge blocking layer contact holes. This extraction simplifies the fabrication process while maintaining transistor functionality through alternative design approaches in the memory cell region.
Solution Approach 2:
The patent segments the device into distinct memory cell region and peripheral circuit region with different structural configurations. The peripheral circuit region uses a simplified structure without charge blocking layer, while the memory cell region maintains the full structure, allowing differentiated processing that reduces overall fabrication complexity.
2Reliability
If charge blocking layer contact hole is formed, then connection between floating gate electrode and control gate electrode is achieved, but interface stability deteriorates and voids may cause short circuits
Solution Approach 1:
By removing the charge blocking layer and control gate electrode in the peripheral circuit region, the patent eliminates the interface between these layers that would require contact holes. This extraction prevents interface instability and void formation while maintaining electrical connection through the simplified structure.
3Reliability
If gate pattern height is maintained with control gate electrode and charge blocking layer, then transistor structure is complete, but voids are generated when filling contact holes with inter-layer insulation layer
Solution Approach 1:
The patent extracts the control gate electrode and charge blocking layer from the peripheral circuit region, reducing gate pattern height and eliminating the need for charge blocking layer contact holes. This prevents void formation during inter-layer insulation layer filling while maintaining complete transistor structure through alternative configurations.
4Reliability
If peripheral circuit region uses typical transistor structure with control gate electrode, then transistor operation is achieved, but signal delay increases and performance deteriorates
Solution Approach 1:
By removing the control gate electrode and charge blocking layer from the peripheral circuit region, the patent reduces the number of interfaces and layers that signals must traverse, thereby reducing signal delay and improving performance while maintaining transistor operation through simplified structures.
Data Source
AI summary
A non-volatile memory device includes a peripheral circuit region and a cell region. A method for fabricating the non-volatile memory device includes forming gate patterns over a substrate, the gate pattern including a tunnel insulation layer, a floating gate electrode, a charge blocking layer and a control gate electrode, and removing the control gate electrode and the charge blocking layer of the gate pattern formed in the peripheral circuit region.