Non-Volatile Memory Gate Stack Width Reduction
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Solution Overview
Problem
Non-volatile memory devices face reliability issues due to process-induced defects and program/erase cycle damage, leading to reduced operational speed and durability, particularly due to non-uniform electrical fields causing damage to the gate insulation layer.
Innovation Solution
A method involving the formation of a patterned gate stack with etched gate insulation and blocking insulation layers, followed by the deposition of material layers to laterally confine the gate stack components, and the creation of spacers to define gaps that reduce the width of these layers, thereby mitigating damage from electrical fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulation layer width is reduced through etching to improve reliability, then the device becomes more resistant to electrical field damage, but the manufacturing process complexity increases
Solution Approach 1:
The gate insulation layer is divided into multiple segments with different widths along the channel length. The etching process creates a non-uniform width profile where the layer is narrower at critical regions (near source/drain) and wider at other regions. This segmentation allows the device to withstand electrical field stress better while managing manufacturing complexity through selective etching.
Solution Approach 2:
Different regions of the gate insulation layer are given different local properties through selective etching. The width of the gate insulation layer varies locally to provide enhanced protection at specific locations where electrical field stress is highest, while maintaining standard width in regions where it is less critical. This local quality optimization improves overall reliability without uniformly increasing process complexity.
2Stability of the object's composition
If material layers are deposited to laterally confine gate stack components, then the structural integrity improves, but the manufacturing time and process steps increase
Solution Approach 1:
Material layers are deposited in advance to form lateral confinement structures before final device assembly. These confinement layers are prepared as part of the gate stack formation process, ensuring structural integrity is established early in manufacturing. By performing this action preliminarily, the patent avoids needing additional complex assembly steps later, thus managing manufacturing time effectively.
3Reliability
If spacers are formed to define gaps and reduce layer width, then the electrical field distribution becomes more uniform, but the number of process steps increases
Solution Approach 1:
Spacers are introduced as intermediary structures that mediate between the gate stack components and the surrounding environment. These spacers define gaps that control the electrical field distribution, preventing direct contact and reducing field concentration at critical interfaces. The spacers act as buffer structures that improve operational durability while adding a manageable number of process steps.
Solution Approach 2:
The patent introduces lateral dimensioning through spacer formation to control electrical field distribution. By creating gaps in the lateral dimension rather than modifying vertical layer thickness, the patent achieves more uniform field distribution. This dimensional approach adds process steps but provides precise control over field geometry without requiring complex volumetric modifications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of memory devices by reducing the impact of program/erase cycles and process-induced defects, maintaining operational speed and durability by distributing the electrical field more uniformly across the device.
Implementation Method 1
performing an etching process on the patterned gate stack to selectively remove at least a portion of each of the gate insulation layer and the blocking insulation layer, the etching process reducing a width of each of the gate insulation layer and the blocking insulation layer from the initial width to a final width
Implementation Method 2
forming at least one material layer proximate sidewalls of the patterned gate stack, the at least one material layer laterally confining each of the gate insulation layer, the charge storage layer, the blocking insulation layer, and the gate electrode
Data Source
AI summary
A method includes forming a patterned gate stack for a memory device, the patterned gate stack including a gate insulation layer, a charge storage layer, a blocking insulation layer and a gate electrode, the gate insulation layer and the blocking insulation layer having an initial width. An etching process is performed on the patterned gate stack to selectively remove at least a portion of each of the gate insulation layer and the blocking insulation layer, the etching process reducing a width of each of the gate insulation layer and the blocking insulation layer from the initial width to a final width. After performing the etching process, at least one material layer is formed proximate sidewalls of the patterned gate stack, the at least one material layer laterally confining each of the gate insulation layer, the charge storage layer, the blocking insulation layer, and the gate electrode.