3D Non-Volatile Memory Gate Stacking for Integration Density
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Solution Overview
Problem
Current non-volatile memory devices face limitations in increasing integration density due to the need for expensive equipment for miniaturization, leading to a desire for three-dimensional configurations to enhance performance and reduce costs.
Innovation Solution
A non-volatile memory device design featuring a substrate with a memory cell region and connection region, including a mold structure with stacked gate electrodes and insulating layers, a channel structure, and a cell contact that is electrically connected to a first gate electrode but not the second, with specific thickness and structural features to improve integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional or planar non-volatile memory device configuration is used, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar configuration to a three-dimensional vertical configuration by stacking multiple gate electrodes (first gate electrode, second gate electrode, third gate electrode) vertically over the channel structure. This vertical stacking enables higher integration density by utilizing the third dimension (height) rather than only the planar area, effectively increasing the quantity of memory cells per unit area while managing device complexity through systematic layering.
2Quantity of substance
If pattern miniaturization is pursued to increase integration density, then integration density improves, but expensive equipment is required
Solution Approach 1:
Instead of pursuing further planar pattern miniaturization which would require expensive lithography equipment, the patent achieves higher integration density by stacking gate electrodes vertically. The first gate electrode is positioned at a first height, the second gate electrode at a second height, and the third gate electrode at a third height, creating a three-dimensional arrangement that increases cell density without requiring advanced planar patterning processes.
Solution Approach 2:
The patent implements a nested structure where multiple gate electrodes are stacked within a vertical column over the same channel region. The first gate electrode nests over the channel, the second gate electrode nests over the first gate electrode, and the third gate electrode nests over the second gate electrode. This nested arrangement maximizes integration density by packing multiple functional layers within a compact vertical space, avoiding the need for expensive planar miniaturization equipment.
3Quantity of substance
If three-dimensional configuration with stacked gate electrodes is used, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent employs a nested doll structure where the first gate electrode, second gate electrode, and third gate electrode are stacked vertically in a nested arrangement. Each gate electrode is positioned at a different height level, creating a compact three-dimensional structure that increases integration density. The insulating layers are also nested between the gate electrodes, providing electrical isolation while maintaining the compact vertical architecture.
Solution Approach 2:
The patent segments the gate structure into multiple discrete gate electrodes (first gate electrode, second gate electrode, third gate electrode) positioned at different heights, rather than using a single continuous gate structure. This segmentation allows for independent control and optimization of each gate electrode, managing device complexity by dividing the overall gate function into manageable segments while achieving higher integration density through vertical stacking.
4Quantity of substance
If vertical stacking of gate electrodes is implemented, then integration density improves, but electrical connection reliability may deteriorate
Solution Approach 1:
The patent introduces insulating layers as intermediary elements between the first gate electrode, second gate electrode, and third gate electrode. These insulating layers are positioned between adjacent gate electrodes in the vertical stack, providing electrical isolation and preventing unwanted electrical interactions. This intermediary structure ensures reliable electrical connections by clearly defining conductive and insulating regions, maintaining signal integrity while enabling high-density vertical stacking.
Data Source
AI summary
A non-volatile memory device includes a substrate, a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers, wherein the plurality of gate electrodes are stacked in a step shape, a channel structure that extends through the mold structure, and a cell contact that extends through the mold structure, the cell contact is connected to a first gate electrode, and the cell contact is not electrically connected to a second gate electrode among the plurality of gate electrodes, wherein the first gate electrode includes: an extension portion; a pad portion having a vertical thickness greater than a vertical thickness of the extension portion; and a connection portion that electrically connects the pad portion to the cell contact, the connection portion has a vertical thickness less than a vertical thickness of the pad portion, and one or more first insulating rings on the connection portion.