Non-volatile Memory Selective Hard Write Control
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Solution Overview
Problem
Non-volatile memory cells often experience write errors due to process variations, requiring higher stress during write operations, which can compromise memory reliability if applied to all cells simultaneously.
Innovation Solution
A non-volatile memory circuit that selectively performs a 'hard write' on error-prone cells by applying higher voltage or current, while other cells undergo a normal write, using a hard write control circuit to identify and manage write error-prone cells during operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher voltage or current is applied to all memory cells during write operations, then write success rate for error-prone cells improves, but reliability of other cells deteriorates due to unnecessary stress
Solution Approach 1:
The patent applies different write conditions to different memory cells based on their individual characteristics. Error-prone cells receive hard writes with higher voltage or current, while normal cells receive standard writes. This is achieved through a hard write control circuit that selectively activates hard write conditions for specific cells, thereby improving write success for problematic cells without subjecting all cells to harmful stress.
2Reliability
If selective hard write is implemented for error-prone cells, then write operation success rate improves, but device complexity increases due to additional control circuitry
Solution Approach 1:
The memory system is segmented into error-prone cells and normal cells, with the hard write control circuit dividing write operations into hard writes and normal writes. This segmentation allows the system to apply appropriate write conditions to each cell type, improving overall write success rate while keeping the additional complexity localized to the control circuit rather than affecting the entire memory system.
Data Source
AI summary
As disclosed herein, a non-volatile memory circuit includes an array of memory cells. The non-volatile memory circuit also includes circuitry for performing a hard write to selective bits of addressed cells simultaneously with a normal write to the other bits of the addressed cells during a write operation to the addressed cells.