Non-volatile Memory Erasure via Hot Hole Generation
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Solution Overview
Problem
Current non-volatile memory erasure methods require high voltages and long times, leading to increased costs and manufacturing difficulties due to the need for a tunneling oxide layer, and fail to achieve low voltage and high speed erasure.
Innovation Solution
A non-volatile memory low voltage and high speed erasure method is achieved by forming a stacked gate structure with a floating gate and control gate separated by a gate dielectric layer, where the drain voltage is greater than the source voltage to generate hot holes, or by using negative voltages to reduce operation voltage and current, thereby increasing erasure speed and reducing voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high erasure voltage (>10V) is used in conventional non-volatile memory, then erasure operation can be performed, but the voltage raising area increases cost and manufacturing complexity
Solution Approach 1:
The patent changes the voltage parameter from conventional high voltage (>10V) to low voltage (0-5V) by modifying the erasure mechanism. Instead of using high voltage directly, the invention applies negative voltage to the control gate and positive voltage to the drain, creating a voltage difference that generates hot holes for erasure at low operating voltages, thereby eliminating the need for voltage raising circuits
Solution Approach 2:
The patent replaces the conventional high-voltage electrical mechanism with a low-voltage mechanism that utilizes hot hole generation through voltage differential. By substituting the direct high-voltage approach with a controlled voltage difference method that generates hot holes, the system achieves erasure functionality without requiring high voltage generation circuitry
2Productivity
If conventional erasure time in the order of milli-second is used, then erasure operation can be completed, but high speed erasure cannot be achieved
Solution Approach 1:
The patent changes the temporal parameter by reducing erasure time from milli-second order to micro-second or sub-micro-second order. This is achieved by using low voltage operation with negative control gate voltage and positive drain voltage to generate hot holes more efficiently, significantly accelerating the erasure process and enabling high-speed memory operation
3Reliability
If tunneling oxide layer is added to reduce oxide layer influence, then erasure voltage and time can be reduced, but manufacturing difficulty and production cost increase
Solution Approach 1:
The patent extracts and eliminates the tunneling oxide layer from the memory structure, achieving erasure functionality without this additional layer. By removing the tunneling oxide requirement, the invention simplifies the manufacturing process and reduces production costs while maintaining the ability to achieve low voltage and high speed erasure through the low voltage hot hole generation mechanism
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method increases erasure speed by 10-100 folds while reducing the required erasure voltage, enabling miniaturization of non-volatile memory and improving reliability through ultra-low operation voltage and current usage.
Implementation Method 1
changing the gate voltage while erasing the memory, such that drain voltage is greater than source voltage, so as to generate adequate hot holes in achieving high speed erasure of memory
Implementation Method 2
The stacked gate structure includes a floating gate and a control gate separated by a gate dielectric layer... changing the gate voltage while erasing the memory
Data Source
AI summary
A non-volatile memory low voltage and high speed erasure method, the non-volatile memory is realized through disposing a stacked gate structure having a control gate and a floating gate on a semiconductor substrate or in an isolation well, such that adequate hot holes are generated in proceeding with low voltage and high speed erasure operation through a drain reverse bias and making changes to gate voltage. In addition, through applying positive and negative voltages on a drain, a gate, and a semiconductor substrate or well regions, adequate hot holes are generated, so as to lower the absolute voltage in achieving the objective of reducing voltage of erasing memory.