Non-Volatile Memory Hybrid Read Erase Operation
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Solution Overview
Problem
Conventional non-volatile memory devices are designed to retain data integrity during read operations, making it difficult to implement one-time access scenarios where data should be erased after being read, which is necessary for applications like pay-per-view content and secure communications.
Innovation Solution
A hybrid read operation is implemented in non-volatile memory cells that allows for simultaneous reading and erasing of data, using a programmable onboard controller to effectuate bias conditions for a single integrated circuit or two-step process, ensuring data is erased after access, utilizing channel hot electron injection to maintain bit-specificity and prevent disturbance to adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional non-volatile memory cells are designed to retain data during read operations, then data integrity is improved, but one-time access capability deteriorates
Solution Approach 1:
The memory device dynamically changes its operational mode based on the type of read operation performed. During a standard read, the device maintains data integrity by using benign biasing conditions. During a one-time access read, the device transitions to a destructive read mode where higher bias conditions are applied that transfer charge from the floating gate, erasing the data after reading. This dynamic adaptation allows the same hardware to serve both conventional and one-time access applications.
Solution Approach 2:
The invention changes the electrical parameters (biasing conditions) applied to the memory cell during read operations. For one-time access, the control gate voltage and drain voltage are set to specific values that enable charge transfer and subsequent data erasure. For standard reads, different voltage parameters are used that preserve the stored charge. This parameter switching enables the memory to provide both data integrity and one-time access functionality.
2Adaptability or versatility
If a hybrid read operation is implemented to erase data after reading, then one-time access capability is improved, but device complexity increases
Solution Approach 1:
The invention merges the read operation and erase operation into a single hybrid read operation. Instead of performing a read followed by a separate erase command, the hybrid read simultaneously completes both functions in one operational sequence. This is achieved by applying specific bias conditions during the read that automatically trigger charge transfer and data erasure, eliminating the need for additional control logic or separate operational steps.
Solution Approach 2:
The memory cell performs the erase function automatically as part of the read operation itself. When a one-time access read is initiated, the bias conditions applied during reading inherently cause charge to be transferred from the floating gate, which both enables the read signal and simultaneously erases the data. The system serves itself by using the read operation's own electrical conditions to accomplish the erasure, without requiring external intervention or additional circuitry.
3Manufacturing precision
If channel hot electron injection is used for bit-specific erasure, then manufacturing precision is improved, but energy consumption increases
Solution Approach 1:
The invention applies local quality by confining the erasure effect to only the specific memory bit being read. By applying the hybrid read operation to a selected word line and bit line intersection, the high bias conditions and resulting charge transfer are localized to that single cell. Adjacent cells on the same word line are not subjected to the same conditions, ensuring that only the targeted bit is erased while others remain intact. This spatial localization achieves precise bit-specific erasure.
Solution Approach 2:
The channel hot electron injection process occurs rapidly during the read operation, transferring charge from the channel to the floating gate in a very short time window. This quick charge transfer accomplishes the erasure function before significant energy can be dissipated or before adjacent cells are affected. The rapid execution of the charge transfer process minimizes energy consumption while maintaining precision in the bit-specific erasure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables one-time accessibility of data, ensuring data is permanently removed after reading, enhancing security and reducing device wear, while maintaining data retention during ambient storage, and is applicable to various non-volatile memory types, including floating gate and Phase Change Memory cells.
Implementation Method 1
A non-volatile memory cell device stores a logic state based on a value of a charge physically present in a memory cell
Implementation Method 2
i) a read of the stored memory cell logic state during a first phase
Implementation Method 3
ii) an erase of the stored memory cell logic state during an immediately subsequent second phase
Implementation Method 4
utilizing channel hot electron injection to maintain bit-specificity and prevent disturbance to adjacent cells
Data Source
AI summary
A programmable non-volatile memory device effectuates two different functions (read, erase (re-program)) during a single instruction or command. During a first phase of the command a cell state is determined by a memory controller circuit, and in a second phase of the same command the cell state is re-written. This implementation is useful for applications where it is desirable to permit one time access only of particular data/content.