Nonvolatile Memory Cell Isolation via High-Concentration Dopant Regions
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory (NVM) cells face issues with charge retention, crystal defects, and electrical defects due to the topography and etching processes associated with thick oxide structures like STI and FOX, which lead to degradation in performance.
Innovation Solution
The use of high-concentration dopant impurity regions formed by ion implantation creates a continuous and planar substrate surface, eliminating the need for STI and FOX structures, thereby reducing crystal defects and sharp edges, and allowing for smaller unit cell sizes and improved integration levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If thick oxide structures (STI or FOX) are used to isolate adjacent floating gate transistors, then isolation between transistors is achieved, but sharp interfaces and topography problems cause charge retention at undesired locations, crystal defects in trench sidewalls, stress defects, and electrical defects that degrade NVM performance
Solution Approach 1:
The patent removes the thick oxide isolation structures (STI and FOX) from the NVM cell design, extracting the problematic element that causes sharp interfaces, topography issues, and crystal defects. Instead of using oxide-based isolation, the invention employs a different approach that eliminates these harmful factors while maintaining transistor isolation functionality
Solution Approach 2:
The patent changes the isolation mechanism from thick oxide structures to a different physical or chemical parameter approach. By altering the isolation method fundamentally, the patent avoids the sharp interfaces and topography problems associated with traditional oxide-based isolation while maintaining effective transistor separation
2Reliability
If STI structures are formed using etching processes to create trenches, then isolation is achieved, but crystal defects are created in the sidewalls of the trenches
Solution Approach 1:
The patent eliminates the etching process and trench formation by removing the STI structure requirement. By extracting the problematic etching step, the patent prevents crystal defects in trench sidewalls while achieving isolation through an alternative method that does not involve creating trenches in the substrate
Solution Approach 2:
The patent replaces the mechanical etching process with a different isolation mechanism that does not require physical trench creation. By substituting the mechanical removal of material with an alternative isolation approach, the patent avoids the crystal defects that result from etching-induced mechanical stress and lattice damage
3Reliability
If sharp interfaces are formed between isolation structures and substrate surface, then isolation is achieved, but power consumption increases due to high current concentrations at sharp edges
Solution Approach 1:
The patent eliminates sharp interfaces by using a isolation approach that creates curved or rounded transitions instead of sharp edges. By applying curvature to the isolation structure interfaces, the patent reduces current concentration effects and associated power consumption while maintaining effective transistor isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data retention, reduces power consumption, and improves disturb characteristics by eliminating sharp edges and stress defects, leading to more reliable and efficient non-volatile memory cells.
Implementation Method 1
The high-concentration dopant impurity regions are formed by ion implantation
Data Source
AI summary
A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.