Nonvolatile Memory Isolation Structure for Erase Field Control

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Solution Overview

Problem

Existing non-volatile memory (NVM) structures face challenges in managing high electric fields during erase operations, which can lead to reduced durability and effectiveness of the memory cells.

Innovation Solution

The implementation of a shallow trench isolation (STI) structure between the erase gate and the source region in the NVM structure helps to limit the electric field experienced by the erase gate oxide, thereby enhancing the structural integrity and operational lifespan of the memory devices.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a shallow trench isolation structure is added between the erase gate and source region, then the durability and functional life of memory devices is improved, but the device complexity and manufacturing steps increase

Engineering Contradiction:
Improvedurability and functional life of memory devicesVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent divides the memory device structure into separate regions by introducing a shallow trench isolation structure between the erase gate and source region. This segmentation isolates high electric field regions from critical components, protecting them while maintaining overall device functionality. The isolation structure creates distinct functional zones that can be independently optimized.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The shallow trench isolation structure acts as an intermediary element between the erase gate and source region. It mediates the interaction between these components by providing electrical isolation and field management, preventing direct exposure of the source region to high electric fields during erase operations while maintaining necessary electrical connections elsewhere.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a shallow trench isolation structure is added between the erase gate and source region, then the effective gate dielectric thickness is increased, but the manufacturing process complexity increases

Engineering Contradiction:
Improveeffective gate dielectric thicknessVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The shallow trench isolation structure is formed preliminarily during the manufacturing process, before final device assembly and operation. By establishing the isolation structure early in the fabrication sequence, the patent ensures proper field management is built into the device architecture from the start, avoiding the need for additional corrective steps later.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent modifies the effective gate dielectric thickness parameter by introducing the isolation structure with specific dimensional characteristics. By controlling the depth, width, and material composition of the shallow trench isolation, the effective dielectric thickness is optimized to provide adequate field management while maintaining compatibility with existing manufacturing capabilities.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The incorporation of the STI structure results in a larger effective gate dielectric thickness for the erase gate, leading to improved durability and extended functional life of the first and second memory devices.

Implementation Method 1

The oxide between the EG and a buried source line of an NVM structure experiences high electric fields during erase operations

Methodology Applied
Scientific EffectElectric Field: Electric Field

Data Source

PatentUS20250133735A1Nonvolatile memory with isolation structure and method of forming the same
Publication Date: 2025.04.24 GLOBALFOUNDRIES US INC
  • US20250133735A1 patent drawing
  • US20250133735A1 patent drawing
  • US20250133735A1 patent drawing

AI summary

A non-volatile memory structure includes a semiconductor substrate and first and second memory devices on the semiconductor substrate. Each of the first and second memory devices includes a floating gate, a tunnelling insulator under the floating gate, an isolation layer over the floating gate, and at least one of a select gate and a control gate over the isolation layer. The non-volatile memory structure further includes an erase gate shared by the first and second memory devices, a source region under the erase gate, and a shallow trench isolation structure between the erase gate and the source region. The shallow trench isolation structure increases the number of write/erase cycles that can be performed by the non-volatile memory structure.