Non-volatile latch using dual NVM cells for low voltage
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Solution Overview
Problem
Conventional non-volatile latches require multiple transistors and have larger chip area, leading to higher costs and inefficiencies, especially when used in applications requiring low voltage operation and data retention.
Innovation Solution
A non-volatile latch design utilizing two independently controllable NVM cells with separate control gates, allowing for programming and erasing operations at low voltages, reducing the number of transistors and chip area by replacing PMOS transistors with NVM cells, and employing CHE and CHH injection methods for state control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SRAM-type latch structure is used, then data retention capability is achieved, but chip area increases and manufacturing cost increases
Solution Approach 1:
The patent merges the latch functionality with NVM cell structure by replacing traditional SRAM transistors with NVM cells. The first and second NVM cells are coupled in series between supply voltages, with their control gates serving as the latch input, thereby combining storage and latching functions into a unified structure that reduces chip area while maintaining data retention.
Solution Approach 2:
The NVM cells serve multiple functions: they act as both the storage element and the latch trigger mechanism. The control gates of the NVM cells function as the latch input, eliminating the need for separate SRAM transistor structures, thereby achieving multi-functionality with reduced component count and area.
2Reliability
If conventional non-volatile latch structure is used, then data retention is achieved, but voltage operation level increases
Solution Approach 1:
The patent changes the operational voltage parameters by utilizing the inherent low-voltage characteristics of NVM cells. The NVM cells can be programmed and erased at relatively low voltages through charge injection mechanisms, allowing the latch to operate at lower voltage levels compared to conventional non-volatile latch designs while maintaining data retention capability.
3Ease of operation
If PMOS transistors are used in latch structure, then latch functionality is achieved, but device complexity and chip area increase
Solution Approach 1:
The patent extracts and removes the PMOS transistors from the traditional latch structure, replacing them with NVM cells. This extraction simplifies the device by eliminating unnecessary components while retaining the essential latch functionality through the series-coupled NVM cell configuration and their control gates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced latch area and lower chip costs while maintaining data retention capabilities, enabling operation at relatively low voltages and efficient state control for various circuit elements.
Implementation Method 1
employing CHE and CHH injection methods for state control
Implementation Method 2
employing CHE and CHH injection methods for state control
Implementation Method 3
The control gate may be capacitively coupled to the floating gate using an oxide-nitride-oxide (ONO) layer
Data Source
AI summary
Methods, circuits, devices, and/or arrangements for providing a non-volatile latch are disclosed. In one embodiment, a non-volatile latch can include: (i) a first non-volatile memory (NVM) cell coupled to a first supply, a first gate (e.g., a control gate), and an output node, where the first NVM cell is configured to be in a first state; and (ii) a second NVM cell coupled to a second supply, a second gate (e.g., another control gate), and the output node, where the second NVM cell is configured to be in a second state.