NVM Latches as External RAM for Edge Computing
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Solution Overview
Problem
Edge computing devices face a challenge in reducing the amount of RAM while still providing adequate volatile memory, as cost-savvy storage flash NAND devices have limited internal static RAM and NVM memory dies with staging buffers called latches are mostly idle during non-storage operations.
Innovation Solution
The latches of NVM dies are dynamically utilized as volatile memory by a controller that notifies and exports them to a processing device for use as RAM, allowing for dual usage as both volatile and non-volatile storage operations, with usage profiles controlling the allocation based on computational needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If cost-savvy storage flash NAND devices are used with limited internal static RAM, then device cost is reduced, but volatile memory capacity becomes insufficient for Edge computing needs
Solution Approach 1:
The latch circuits are designed to perform dual functions: serving as staging buffers for non-volatile memory storage operations and as volatile memory for computational operations. The controller dynamically allocates and manages these latches to fulfill both storage and volatile memory requirements, eliminating the need for separate dedicated volatile memory components and thereby reducing overall device cost while maintaining adequate volatile memory capacity.
2Adaptability or versatility
If latches are used exclusively for non-volatile storage operations, then storage reliability is maintained, but volatile memory availability for computational operations is limited
Solution Approach 1:
The system implements dynamic latch allocation where the controller can switch between different operational modes based on computational needs. During non-storage operations, latches are dynamically repurposed as volatile memory for computational tasks. The controller monitors operational states and dynamically reconfigures latch usage to balance between maintaining storage reliability and providing volatile memory availability, allowing seamless transition between storage and computational modes.
3Quantity of substance
If more internal static RAM is added to NVM devices, then volatile memory capacity increases, but device cost and complexity increase
Solution Approach 1:
The latch circuits, which are already an integral part of the non-volatile memory architecture, are made self-serving by enabling them to provide volatile memory functionality in addition to their primary storage buffer role. This eliminates the need for separate volatile memory components and reduces overall device complexity. The existing latch infrastructure is leveraged to meet volatile memory requirements, avoiding additional complexity that would arise from integrating separate RAM modules or increasing static RAM capacity.
Data Source
AI summary
Non-volatile memory (NVM) dies of a data storage device, wherein on-chip latches of the dies are made available to a host device for use as volatile memory. In some examples, a data storage controller dynamically determines when the latches of a particular NVM die of an NVM array are available for use as volatile memory and exports those particular latches to the host device for use as random access memory (RAM). In other examples, the data storage controller dynamically determines when particular dies of the NVM array of dies are available and exports all latches of those dies to the host device for use as RAM. The data storage controller may rotate NVM die usage so that, over time, different dies are used for latch-based volatile memory while other dies are used for NVM storage. Usage profiles are described that allow the host device to select particular latch usage configurations.