Non-volatile Memory Device Logic Circuit Data Backup
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Solution Overview
Problem
Traditional logic memory circuits require continuous power to maintain data in standby mode, leading to high power consumption, while non-volatile memory devices cannot match the operating speed of logic memory circuits.
Innovation Solution
A non-volatile memory device integrating a logic memory circuit and a non-volatile memory element using a specific architecture, where the writing circuit backs up data from the logic memory circuit to the non-volatile memory element during power-off and restores it during power-on, disabling the writing circuit and enabling the reading circuit during these periods to avoid interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a traditional logic memory circuit is used to maintain data in standby mode, then the data can be kept accessible, but the power consumption increases considerably
Solution Approach 1:
The patent applies preliminary action by backing up data from the logic memory circuit to the non-volatile memory device before entering standby mode. This pre-positioning of data in non-volatile memory allows the system to power down the logic memory circuit while preserving data accessibility upon wake-up, thus resolving the contradiction between data accessibility and power consumption.
Solution Approach 2:
The patent introduces a non-volatile memory device as an intermediary between the logic memory circuit and the power source. This intermediary stores data when the logic memory circuit is powered down, enabling data persistence without continuous power supply to the logic memory circuit, thereby reducing power consumption while maintaining data accessibility.
2Use of energy by moving object
If a traditional non-volatile memory device is used to replace the logic memory circuit, then power consumption is reduced to zero in standby mode, but the operating speed cannot match the logic memory circuit
Solution Approach 1:
The patent segments the memory system into two distinct parts: a logic memory circuit for high-speed data processing during active mode, and a non-volatile memory device for data storage during standby mode. This segmentation allows each component to operate in its optimal performance regime, with the logic memory circuit providing high operating speed when powered and the non-volatile memory providing zero power consumption when the logic memory is powered down.
Solution Approach 2:
The patent implements dynamic operation by switching between two operational states: active mode where the logic memory circuit operates at high speed with full power, and standby mode where the logic memory circuit is powered down and data is stored in non-volatile memory. This dynamic state transition allows the system to optimize between speed and power consumption based on operational requirements.
3Reliability
If the writing circuit continuously backs up data to the non-volatile memory element, then data safety is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent applies periodic action by implementing a writing circuit that operates at specific intervals or triggers rather than continuously. The writing circuit activates periodically to backup data from the logic memory circuit to the non-volatile memory element, and remains inactive during normal operation. This periodic operation reduces power consumption and simplifies the control logic compared to continuous backup, while still maintaining data safety.
Data Source
AI summary
A non-volatile memory (NVM) device includes a logic memory circuit, a NVM element, a writing circuit and a reading circuit. The input terminal of the writing circuit and the output terminal of the reading circuit are coupled to the output terminal of the logic memory circuit. The first output terminal of the writing circuit and the first input terminal of the reading circuit are coupled to the first terminal of the NVM element. The second output terminal of the writing circuit and the second input terminal of the reading circuit are coupled to the second terminal of the NVM element. During a writing period, the writing circuit writes the stored data of the logic memory circuit into the NVM element. During a reading period, the reading circuit restores the data of the NVM element to the output terminal of the logic memory circuit.