NVM Logic Drive Multi-Chip Package for Lower FPGA-to-ASIC NRE
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Solution Overview
Problem
The high cost and inefficiency of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific IC (ASIC) or Customer-Owned Tooling (COT) chips, particularly due to increased Non-Recurring Engineering (NRE) costs and larger chip sizes, power consumption, and lower performance in advanced semiconductor technology nodes, hinder innovation and scalability.
Innovation Solution
Employing a standardized commodity logic drive comprising plural FPGA IC chips with non-volatile random access memory cells, allowing for field programming and reducing NRE costs by a factor of 2 to 10, and utilizing a multi-chip package with optimized chip designs and minimal control/I/O circuits to leverage advanced semiconductor technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transitioning from FPGA to ASIC or COT chips for volume applications, then performance and power efficiency are improved, but Non-Recurring Engineering (NRE) costs and chip design complexity increase significantly
Solution Approach 1:
The patent implements dynamic reconfigurability in ASIC chips through integrated FPGA-like logic blocks and configuration memory, allowing the chip to change its logic functionality after fabrication. This dynamic capability enables the same physical chip to serve multiple application-specific purposes, reducing the need for different ASIC designs for different applications while maintaining the power efficiency of dedicated hardware.
Solution Approach 2:
The patent creates a universal ASIC platform that can be programmed to perform multiple logic functions. By incorporating configuration memory and programmable logic blocks within the ASIC structure, a single chip design can be adapted to serve various application-specific needs, thereby reducing overall device complexity and NRE costs across multiple products while maintaining the power efficiency benefits of ASIC technology.
2Speed
If migrating to advanced semiconductor technology nodes (below 20nm) for ASIC/COT chips, then performance is improved, but NRE costs and fabrication complexity increase dramatically
Solution Approach 1:
The patent enables dynamic reconfiguration capabilities in advanced-node ASIC chips, allowing post-fabrication adaptation to different applications. This reduces the need for costly mask set revisions and NRE investments when migrating to advanced technology nodes, as the same physical chip can be reprogrammed for different logic functions, thereby improving ease of manufacture despite the complexity of advanced node fabrication.
3Adaptability or versatility
If using standard commodity FPGA IC chips for logic functions, then adaptability and flexibility are improved, but chip size, power consumption, and performance are worsened compared to ASIC
Solution Approach 1:
The patent applies local quality by implementing reconfigurable logic blocks only in specific regions of the ASIC chip where adaptability is needed, while other regions maintain fixed, optimized ASIC structures. This localized reconfigurability provides programming flexibility for specific functions while maintaining the low power consumption and high performance of dedicated ASIC hardware for other critical functions, thus resolving the trade-off between adaptability and power efficiency.
Data Source
AI summary
A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.