NVM Logic Drive Packaging for Lower-Cost Field-Programmable ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The high cost and inefficiency of transitioning from Field Programmable Gate Arrays (FPGA) to Application Specific ICs (ASICs) or Customer-Owned Tooling (COT) chips, particularly due to larger chip size, higher fabrication costs, and increased Non-Recurring Engineering (NRE) expenses, hinder innovation in advanced semiconductor technology nodes.
Innovation Solution
Utilizing standardized commodity FPGA IC chips with non-volatile memory cells and programmable logic blocks, allowing for field programming and reducing NRE costs by a factor of 2 to 10, enabling innovation and workload acceleration in advanced semiconductor technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability and ease of operation are improved, but chip size, fabrication cost, and power consumption increase
Solution Approach 1:
The FPGA chip is divided into multiple programmable logic blocks (PLBs) that can be independently configured. Each PLB contains lookup tables (LUTs) and flip-flops that can be programmed to perform different logic functions, allowing the chip to be segmented into functional units that can be customized for specific applications while reducing the overall chip area required for a given functionality.
Solution Approach 2:
The patent implements universal logic blocks that can be programmed to perform multiple different logic functions through configuration memory. The same physical hardware structure can be reconfigured to implement various digital circuits, making the chip multi-functional and adaptable to different applications without requiring separate dedicated circuits for each function.
2Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but fabrication cost increases
Solution Approach 1:
The patent changes the state parameters of the logic blocks from fixed to programmable by introducing configuration memory elements. The logic blocks can be programmed by changing the values stored in configuration SRAM cells or non-volatile memory, allowing post-fabrication customization without requiring expensive custom fabrication processes for each application.
Solution Approach 2:
The FPGA chip is fabricated with all necessary logic blocks, interconnects, and configuration memory structures in advance during the standard FPGA manufacturing process. This preliminary action enables field programming capability to be built into the chip architecture before deployment, eliminating the need for expensive custom ASIC fabrication while maintaining adaptability.
3Adaptability or versatility
If FPGA IC chips are used for field programming purposes, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamically reconfigurable logic blocks that can change their function and connectivity during operation. The configuration memory allows the logic blocks to be reprogrammed in the field to adapt to changing computational requirements, enabling the system to optimize power consumption by activating only the necessary logic functions for each specific task rather than running all logic blocks continuously.
Data Source
AI summary
A multi-chip package includes: an interposer; a first IC chip over the interposer, wherein the first IC chip is configured to be programmed to perform a logic operation, comprising a NVM cell configured to store a resulting value of a look-up table, a sense amplifier having an input data associated with the resulting value from the NVM cell and an output data associated with the first input data of the sense amplifier, and a logic circuit comprising a SRAM cell configured to store data associated with the output data of the sense amplifier, and a multiplexer comprising a first set of input points for a first input data set for the logic operation and a second set of input points for a second input data set having data associated with the data stored in the SRAM cell, wherein the multiplexer is configured to select, in accordance with the first input data set, an input data from the second input data set as an output data for the logic operation; and a second IC chip over the interposer, wherein the first IC chip is configured to pass data associated with the output data for the logic operation to the second IC chip through the interposer.