NVM Logic Integration via Gate-First Hard Masking
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Solution Overview
Problem
The integration of non-volatile memory (NVM) transistors with logic transistors is challenging due to different requirements for charge storage, particularly with unique layers like floating gates, nanocrystals, or nitride, which complicate their integration.
Innovation Solution
A method is developed where the gate structure of NVM cells is formed with a charge storage layer while masking the logic portion, using a hard mask to create sidewall spacers, and simultaneous source/drain implants are performed in both NVM and logic portions, allowing for the integration of metal gate transistors alongside NVM cells using nanocrystals without contamination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If unique charge storage layers (floating gate, nanocrystals, or nitride) are used in NVM transistors, then charge storage capability is improved, but integration with logic transistors becomes difficult
Solution Approach 1:
The patent divides the integrated circuit into distinct NVM portions and logic portions, allowing each to be optimized independently. The NVM cells use unique charge storage layers (nanocrystals, floating gates, or nitride) while logic transistors use standard CMOS structures, reducing integration complexity while maintaining charge storage capability.
Solution Approach 2:
The patent develops a universal fabrication methodology that can accommodate multiple types of charge storage layers (nanocrystals, floating gates, nitride) within the same process flow. This multi-functional approach allows flexible integration of different NVM technologies with logic transistors without requiring separate fabrication lines.
2Reliability
If NVM transistors are formed with charge storage layers, then non-volatile memory functionality is achieved, but contamination of logic portions occurs
Solution Approach 1:
The patent employs selective masking to spatially separate NVM and logic portions during fabrication. The logic portions are masked during NVM cell formation processes, preventing contamination from charge storage layer materials while allowing NVM functionality to be fully implemented in unprotected regions.
Solution Approach 2:
The patent uses masking layers as intermediary protective barriers between NVM and logic portions. These masks act as mediators that allow the fabrication process to proceed without direct interaction between NVM charge storage materials and logic transistor structures, preventing contamination.
3Reliability
If different fabrication requirements for NVM and logic transistors are accommodated, then device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent creates a universal fabrication methodology that integrates multiple specialized processes into a single coherent flow. The same basic process steps can form both NVM cells with various charge storage layers and logic transistors, reducing manufacturing complexity while maintaining optimized performance for each device type.
Solution Approach 2:
The patent combines the fabrication of NVM cells and logic transistors into a single integrated process sequence. By merging previously separate fabrication flows into one unified methodology with selective masking, the patent reduces the overall number of discrete process steps while accommodating different device requirements.
Data Source
AI summary
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.