Gate-Last NVM Logic Integration via Hard Mask Protection
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Solution Overview
Problem
The integration of non-volatile memory (NVM) transistors with logic transistors is challenging due to different requirements for charge storage, which complicates their co-integration, especially when using unique charge storage layers like floating gates, nanocrystals, or nitride, affecting available integration options.
Innovation Solution
A method is developed where the gate structure of NVM cells is formed with a charge storage layer while masking the logic region, using hard masks to create sidewall spacers, and then simultaneously performing source/drain implants in both regions, protecting NVM cells during metal gate processing to ensure effective integration and electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge storage layers (floating gates, nanocrystals, or nitride) are used in NVM transistors, then charge storage capability is improved, but integration complexity with logic transistors increases
Solution Approach 1:
The patent divides the integrated circuit into distinct NVM regions and logic regions, allowing each to be processed independently with region-specific masks. This segmentation enables the complex NVM charge storage layers to coexist with logic transistors without requiring the entire circuit to follow the more complex NVM fabrication sequence.
Solution Approach 2:
The patent applies different processing conditions to different regions: NVM regions receive charge storage layer deposition and specific doping, while logic regions receive standard logic transistor processing. This local quality approach allows each region to have optimized structures without compromising the other.
2Speed
If standard logic transistor processing is performed, then logic transistor speed is improved, but contamination of NVM charge storage layers may occur
Solution Approach 1:
The patent introduces hard masks as intermediary protective layers during processing. These masks physically separate the NVM charge storage layers from logic region processing steps, preventing contamination while allowing logic transistor fabrication to proceed with standard high-speed processes.
Solution Approach 2:
The patent applies protective masks to NVM regions before logic transistor processing begins. This preliminary protective action prevents potential contamination from occurring in the first place, allowing subsequent high-speed logic processing without compromising NVM charge storage integrity.
3Reliability
If region-specific masking is performed during gate formation, then electrical isolation between NVM and logic regions is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent designs hard masks to serve multiple functions: they protect NVM charge storage layers during logic processing, define region boundaries for electrical isolation, and can be removed uniformly after processing. This multi-functionality reduces the need for separate dedicated structures for each purpose.
Solution Approach 2:
The patent combines the electrical isolation function with the protective masking function into a single integrated approach. The same hard mask structures that protect during processing also serve as the isolation barriers, merging two functions into one unified solution rather than requiring separate structures.
Data Source
AI summary
A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM region and a first protection layer over a logic region. A control gate and a storage layer are formed over the substrate in the NVM region. The control gate has a top surface below a top surface of the select gate. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The first and second protection layers are removed from the logic region. A portion of the second protection layer is left over the control gate and the select gate. A gate structure, formed over the logic region, has a high k dielectric and a metal gate.