NVM and Logic Transistor Integration via Dummy Gate Process
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Solution Overview
Problem
The integration of non-volatile memory (NVM) cells with metal gate/high-k dielectric logic transistors on the same integrated circuit requires numerous additional process steps, complicating the manufacturing process.
Innovation Solution
A method is developed to efficiently integrate NVM cells with metal gate/high-k dielectric logic transistors by forming a charge storage layer with nanocrystals, using a high-k dielectric layer, and employing a dummy gate process where the work function setting material is retained while the dummy top gate is replaced by the final top gate, allowing for flexible choices in storage and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM cells are integrated with metal gate/high-k dielectric logic transistors using conventional processes, then both device types can be embedded on the same integrated circuit, but the manufacturing process requires numerous additional process steps
Solution Approach 1:
The patent divides the integrated circuit into distinct NVM regions and logic regions with separate process flows. The NVM cells and logic transistors are fabricated independently using their respective optimized processes, then integrated through controlled interconnections. This segmentation allows each device type to be manufactured with standard processes while achieving integration, thereby reducing overall process complexity.
Solution Approach 2:
The patent introduces intermediate structures such as isolation layers, interconnect layers, and buffer regions that mediate between the NVM cell structures and logic transistor structures. These intermediary elements facilitate compatibility between the two different device types without requiring modification of their core fabrication processes, thus reducing the number of additional process steps needed.
2Reliability
If conventional integration methods are used for NVM and logic transistors, then both can coexist on the same chip, but many additional process steps are required
Solution Approach 1:
The patent performs preliminary actions by pre-defining region boundaries, pre-forming isolation structures, and pre-establishing interconnect pathways before the main integration process. This preliminary preparation allows subsequent fabrication steps to proceed more efficiently without requiring complex real-time adjustments, thereby improving manufacturing productivity while maintaining device compatibility.
Solution Approach 2:
The patent applies local quality by tailoring specific process parameters, material compositions, and structural configurations to the requirements of each region (NVM vs. logic). This localized optimization allows each device type to be fabricated with its ideal process parameters while maintaining overall integration, reducing the need for additional compromise process steps.
Data Source
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AI summary
A first conductive layer (30) and an underlying charge storage layer (20) are patterned to form a control gate (32) in an NVM region (12). A first dielectric layer (34) and barrier layer (35) are formed over the control gate. A sacrificial layer (36) is formed over the barrier layer and planarized. A first patterned masking layer (38) in the NVM region defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer (38) defines a logic gate location in the logic region (14). Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location and a second portion remains at the logic gate location. A second dielectric layer (52) is formed over, and planarized to expose, the first and second portions. The first and second portions are removed to result in openings at the select gate location and at the logic gate location which expose the barrier layer.