NVM-Logic Interface Repeatable Structure for Defect Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of non-volatile memory (NVM) cells with other circuit elements often results in issues such as defects and difficulties in achieving a repeatable structure, leading to false defect detections and increased photoresist thickness requirements, which can hinder the design process.
Innovation Solution
A method involving the etching of a second polysilicon layer over a first polysilicon layer at the interface between an array area and a logic area, creating a repeatable structure of single polysilicon layer height, which is recognized as an intentional feature rather than a defect, reducing false detections and allowing for thinner photoresist usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM cells are integrated with other circuit elements using standard processes, then integration is achieved, but defects and false defect detections occur due to non-repeatable structures
Solution Approach 1:
The patent applies local quality by creating a specific repeatable structure at the interface between NVM array area and logic area. This localized structural feature ensures that the interface region has consistent, identifiable characteristics that distinguish it from actual defects, thereby improving defect detection accuracy while maintaining integration capability.
Solution Approach 2:
The patent uses copying by creating a repeatable structure that replicates a known good pattern at the NVM-logic interface. This copied structure serves as a reference template that defect detection equipment can recognize, allowing differentiation between intentional structures and actual defects.
2Manufacturing precision
If thicker photoresist is used to accommodate integration structures, then coverage is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies parameter changes by modifying the structural parameters at the NVM-logic interface to create a repeatable pattern. This structural modification ensures that standard photoresist thicknesses are sufficient for proper coverage, eliminating the need for thicker photoresist layers and associated manufacturing complexities.
3Adaptability or versatility
If non-repeatable structures are formed during NVM integration, then design flexibility is maintained, but false defect detections increase
Solution Approach 1:
The patent applies local quality by creating a specific repeatable structure at the interface between NVM array area and logic area. This localized structural feature ensures that the interface region has consistent, identifiable characteristics that distinguish it from actual defects, thereby improving defect detection accuracy while maintaining integration capability.
Solution Approach 2:
The patent uses copying by creating a repeatable structure that replicates a known good pattern at the NVM-logic interface. This copied structure serves as a reference template that defect detection equipment can recognize, allowing differentiation between intentional structures and actual defects.
Data Source
AI summary
A feature is formed in the NVM isolation region during the patterning and etching of an NVM device and a logic device such that the feature is of substantially equal height to the logic device and is well-defined so that it does not cause defect signals. A first conductive layer is formed over a substrate. The first conductive layer is patterned to expose at least a portion of the substrate in an NVM region and at least a portion of an isolation region. An NVM dielectric stack is formed over the first conductive layer, the exposed substrate, and the exposed isolation region, and a second conductive layer is formed over the NVM dielectric stack. The first and second conductive layers and the NVM dielectric stack are patterned to form a first gate and a second gate of an NVM cell in the NVM region and a feature over the isolation region. The feature comprises a portion of the first conductive layer, a portion of the NVM dielectric stack adjacent a first sidewall of the portion of the first conductive layer, and a portion of the second conductive layer adjacent the portion of the NVM dielectric stack.