NVM-Logic Chip Integration With Fewer Photomask Steps
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Solution Overview
Problem
The integration of nonvolatile memory (NVM) devices and logic devices in a single chip is complex due to structural differences, requiring multiple photo lithography masks, which increases manufacturing costs and complexity.
Innovation Solution
A semiconductor device and manufacturing method that integrate NVM and logic devices using a reduced number of photo mask processes, allowing for simultaneous formation of logic devices and NVM devices on a single chip, with shared processing steps to reduce the number of masks and processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photo lithography masks are used to integrate NVM and logic devices, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the formation of NVM devices and logic devices into a unified manufacturing process. By combining previously separate photo lithography steps into a single integrated process, the patent reduces the number of masks required while maintaining the precision needed for both device types. This is achieved through shared processing steps and coordinated patterning that simultaneously defines both NVM and logic device structures.
Solution Approach 2:
The patent creates a universal manufacturing process that serves multiple functions: it forms both NVM devices and logic devices using the same photo lithography masks and processing steps. The process is designed to be multi-functional, handling different device types with a single integrated approach rather than requiring separate specialized processes for each device type.
2Manufacturing precision
If multiple photo lithography masks are used to integrate NVM and logic devices, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines multiple photo lithography steps into a reduced number of integrated steps, directly reducing the number of masks that need to be manufactured and applied. This merging of steps reduces both material costs (fewer masks) and processing costs (fewer deposition and etching cycles), while maintaining the required precision through coordinated patterning designs.
Solution Approach 2:
The patent modifies process parameters such as photo lithography exposure conditions, etching selectivity, and deposition thicknesses to enable a single integrated process to achieve the precision previously requiring multiple steps. By optimizing these parameters, the patent maintains manufacturing precision while reducing the number of required masks and processing steps.
3Manufacturing precision
If multiple photo lithography masks are used to integrate NVM and logic devices, then manufacturing precision is improved, but processing time increases
Solution Approach 1:
The patent merges sequential photo lithography steps into a combined simultaneous process, reducing the total number of deposition and etching cycles required. By integrating the formation of NVM and logic devices into a unified process flow, the patent eliminates the time lost in transitioning between separate manufacturing steps while maintaining precision through coordinated patterning.
Solution Approach 2:
The patent performs preliminary planning and design of the integrated structure before manufacturing, allowing the photo lithography masks to be designed to simultaneously define both NVM and logic device features in a single exposure step. This preliminary design work enables the subsequent manufacturing process to proceed more quickly without sacrificing precision.
Data Source
AI summary
A semiconductor device include a nonvolatile memory device, including a first well region formed in a substrate, a tunneling gate insulator formed on the first well region, a floating gate formed on the tunneling gate insulator, a control gate insulator formed on the substrate, a control gate formed on the control gate insulator, and a first source region and a first drain region formed on opposite sides of the control gate, respectively, and a first logic device, including a first logic well region formed in the substrate, a first logic gate insulator formed on the first logic well region, a first logic gate formed on the first logic gate insulator, wherein the first logic gate comprises substantially a same material as a material of the control gate of the nonvolatile memory device.