NVM and Logic Transistor Integration via Segmented Processing
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Solution Overview
Problem
The integration of non-volatile memory (NVM) cells with logic transistors is challenging due to different requirements, particularly with high k gate dielectrics and high voltage transistors, where the high k dielectrics cannot withstand high temperatures and thick oxide layers cause leakage issues by exposing transistor region sidewalls.
Innovation Solution
A method is developed to integrate NVM cells and logic transistors by forming the gate structure of the NVM cell with a charge storage layer while masking the logic portion, using a hard mask for sidewall spacers, and performing simultaneous source/drain implants, which includes growing oxide layers, patterning, and etching to minimize the impact on isolation regions and control the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high k gate dielectrics are used in logic transistors, then transistor performance is improved, but the dielectrics cannot withstand high temperatures required for NVM cell processing
Solution Approach 1:
The integrated circuit is divided into distinct NVM portion and logic portion, allowing each to be processed under its optimal temperature conditions. The NVM portion can undergo high-temperature processing while the logic portion with high k gate dielectric is protected from excessive heat exposure.
Solution Approach 2:
Different temperature processing conditions are applied to different regions of the integrated circuit. The NVM portion receives high-temperature treatment while the logic portion receives controlled temperature treatment, allowing each region to have its own optimal processing parameters.
2Reliability
If thick oxide layers are used in high voltage transistors, then voltage handling capability is improved, but etching these layers exposes sidewall surfaces causing threshold voltage control issues and leakage
Solution Approach 1:
A first conductive layer is deposited over the thick oxide layer to act as an intermediary that prevents direct exposure of the sidewall surface during subsequent etching processes. This intermediate layer allows the thick oxide to be present for voltage handling while preventing the leakage issues that would result from exposing the sidewalls.
Solution Approach 2:
The first conductive layer is deposited in advance before the oxide etching process, preparing the structure to prevent sidewall exposure and threshold voltage control issues before they can occur.
3Productivity
If simultaneous source/drain implants are performed in NVM and logic portions, then manufacturing efficiency is improved, but process control becomes more challenging
Solution Approach 1:
The implant process is segmented into multiple sequential steps with different masks for the NVM portion and logic portion. This allows simultaneous implants to be performed in a controlled manner, maintaining precision while achieving the productivity benefits of combined processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for effective integration of NVM cells and logic transistors with minimal leakage and controlled threshold voltage, addressing the challenges of high k gate dielectrics and high voltage transistors by maintaining coplanarity and reducing the impact of oxide etches on isolation regions.
Implementation Method 1
growing an oxide layer on a major surface of the substrate
Implementation Method 2
forming the gate structure of the NVM cell in the NVM portion, including the charge storage layer
Data Source
AI summary
A method of making a semiconductor structure using a substrate having a non-volatile memory (NVM) portion, a first high voltage portion, a second high voltage portion and a logic portion, includes forming a first conductive layer over an oxide layer on a major surface of the substrate in the NVM portion, the first and second high voltage portions, and logic portion. A memory cell is fabricated in the NVM portion while the first conductive layer remains in the first and second high voltage portions and the logic portion. The first conductive layer is patterned to form transistor gates in the first and second high voltage portions. A protective mask is formed over the NVM portion and the first and second high voltage portions. A transistor gate is formed in the logic portion while the protective mask remains in the NVM portion and the first and second high voltage portions.