NVM and Logic Transistor Integration Using Selective High-k Dielectric Processing
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Solution Overview
Problem
The integration of non-volatile memory (NVM) cells with metal gate/high-k dielectric logic transistors on the same integrated circuit requires numerous additional process steps, complicating the manufacturing process.
Innovation Solution
A method is developed to form non-volatile memory cell transistors and CMOS logic transistors using polysilicon and metal layers, where the NVM cell floating gate or select gate is formed from a first polysilicon layer and the control gates of the NVM and logic transistors are formed from a second polysilicon or metal layer, with a high-k gate dielectric layer used for the logic transistor region, and an ONO or nanocrystal layer as a charge storage layer in place of a floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM cells are integrated with metal gate/high-k dielectric logic transistors on the same integrated circuit, then functionality of both NVM and logic transistors is maintained, but the number of process steps increases significantly
Solution Approach 1:
The patent divides the integrated circuit into distinct NVM regions and logic regions with separate process flows. The NVM cells use traditional polysilicon gate processes while logic transistors receive high-k dielectric and metal gate layers, allowing each region to be optimized independently without requiring all regions to follow the most complex process sequence
Solution Approach 2:
The patent applies different gate dielectric and gate material structures to different regions of the substrate. The high-k dielectric layer and metal gate layer are formed only in the logic transistor region, while the NVM region maintains its original polysilicon gate structure, allowing each region to have the appropriate structure for its function without unnecessary complexity elsewhere
2Ease of manufacture
If traditional NVM integration processes are used, then manufacturing process is simpler, but compatibility with metal gate/high-k dielectric logic transistors is poor
Solution Approach 1:
The patent forms the high-k dielectric layer and metal gate layer in the logic region before forming the NVM cell structures. This preliminary action allows the logic transistor region to be prepared in advance with the appropriate gate structure, and subsequent NVM processing steps can proceed without requiring modification of these already-formed layers
Solution Approach 2:
The patent uses selective masking and region-specific processing as intermediaries to bridge between the simple NVM process and the complex metal gate/high-k dielectric logic process. The masking layers and selective etching/deposition steps act as intermediaries that allow both process types to coexist on the same substrate without requiring full integration of all process steps
Data Source
AI summary
Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned.