Non-volatile Memory Mapping Table Segmentation for Startup Recovery

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Solution Overview

Problem

Conventional SSDs face significant startup delays after abnormal power-off events due to the time-consuming process of rebuilding the mapping table, which is exacerbated by large memory capacities, leading to prolonged access command response times.

Innovation Solution

The proposed solution involves dividing the mapping table into sub-mapping tables based on logical address groups, allowing for selective rebuilding of only the required sub-mapping tables during startup, rather than the entire mapping table, thereby reducing the rebuilding time and improving startup speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the mapping table is stored in the DRAM to enhance access speed, then the access speed is improved, but the mapping table contents will be lost when power is provided to the SSD after abnormal power-off event

Engineering Contradiction:
Improveaccess speedVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The mapping table is divided into multiple sub-mapping tables based on logical address groups. Each sub-mapping table can be independently managed and rebuilt, reducing the overall impact of data loss and enabling selective reconstruction after power restoration.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mapping table is pre-divided into sub-mapping tables before power-off events occur. This segmentation is prepared in advance so that when abnormal power-off happens, the system can quickly identify and rebuild only the affected sub-mapping tables rather than the entire mapping table.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the conventional SSD rebuilds the whole mapping table after abnormal power-off event, then the mapping table is restored, but the startup time is prolonged significantly

Engineering Contradiction:
Improvemapping table restorationVSAvoidstartup time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The mapping table is segmented into multiple sub-mapping tables corresponding to different logical address groups. After abnormal power-off, only the specific sub-mapping tables that contain invalid or lost data need to be rebuilt, rather than reconstructing the entire mapping table, thus significantly reducing startup time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing a complete mapping table rebuild (excessive action), the system performs partial rebuilding only of the necessary sub-mapping tables that were affected by the power-off event, achieving the minimum required action to restore functionality.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If the SSD scans all flash memory chips and physical blocks to rebuild the mapping table, then the mapping table is accurately reconstructed, but the rebuilding process becomes time-consuming

Engineering Contradiction:
Improvemapping table accuracyVSAvoidrebuilding efficiency
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The flash memory is divided into multiple chips and blocks, and the mapping table is segmented into sub-mapping tables. During rebuilding, the system only needs to scan the specific blocks associated with the affected sub-mapping tables, rather than scanning all flash memory chips and blocks, thus improving rebuilding efficiency while maintaining accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different sub-mapping tables correspond to different logical address groups and can be rebuilt independently. The system applies different rebuilding actions to different sub-mapping tables based on their specific status, rather than applying a uniform scanning process to all data, thereby optimizing the rebuilding process.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9218280B2Non-volatile memory apparatus and operating method thereof
Publication Date: 2015.12.22 VIA TECH INC
  • US9218280B2 patent drawing
  • US9218280B2 patent drawing
  • US9218280B2 patent drawing

AI summary

A non-volatile memory (NVM) apparatus and an operation method thereof are provided. A mapping table in a main memory is divided into a plurality of sub-mapping tables according to logical address groups. When an access command of a host is processed by the NVM apparatus, at least one corresponding sub-mapping table is selected from the sub-mapping tables according to a logical address of the access command. If the at least one corresponding sub-mapping table is required to be rebuilt, then the at least one corresponding sub-mapping table is rebuilt, and the logical address of the access command is converter for accessing the NVM apparatus according to the at least one corresponding sub-mapping table which has been rebuilt.