Non-Volatile Memory Power Management via Mapping Table Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory systems face high power consumption due to the use of volatile memory for address mapping tables, particularly in systems like flash memory, which increases standby and operating currents, leading to increased power usage in devices like portable electronics.
Innovation Solution
A non-volatile memory system that partitions its memory into a code region, a general-purpose region, and separate mapping table regions, where the mapping tables are loaded into volatile memory only when necessary, allowing for independent power management of different memory types to reduce power consumption by delaying the power-up of less frequently used memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory is used for address mapping tables, then access speed is improved, but power consumption increases
Solution Approach 1:
The patent segments the address mapping table into multiple parts distributed across different memory types. Specifically, it divides the mapping table between volatile memory (for frequently accessed portions) and non-volatile memory (for less frequently accessed portions), allowing the system to benefit from fast access when needed while consuming less power during idle or low-activity periods.
Solution Approach 2:
The patent implements dynamic power management by selectively powering on or off portions of the volatile memory based on system activity. The controller can put idle mapping table segments into a low-power state or transfer them to non-volatile memory, dynamically adjusting the balance between access speed and power consumption according to actual system needs.
2Quantity of substance
If large-capacity DRAM is used for address mapping tables, then mapping capacity is improved, but standby current increases
Solution Approach 1:
The patent divides the large-capacity mapping table into segments that can be stored in non-volatile memory when not in use. This segmentation allows the system to maintain large mapping capacity while only activating the necessary portions in DRAM when needed, thereby reducing standby current consumption.
Solution Approach 2:
The patent extracts the less frequently accessed portions of the mapping table from the volatile DRAM and stores them in non-volatile memory. This extraction reduces the amount of data that needs to be continuously powered in DRAM, thereby lowering standby current while maintaining full mapping capacity when required.
3Speed
If mapping table is continuously loaded in volatile memory, then access speed is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic loading and unloading of mapping table segments based on access patterns and system state. The controller can load frequently accessed mapping table portions into volatile memory for fast access while unloading or powering down less frequently accessed portions, creating a dynamic balance between access speed and power consumption.
Solution Approach 2:
The patent employs periodic refresh or reloading of mapping table segments from non-volatile memory to volatile memory based on usage patterns. Instead of continuously maintaining the entire mapping table in volatile memory, the system periodically loads only the necessary segments, reducing power consumption while maintaining access performance when needed.
Data Source
AI summary
A non-volatile memory system and a method of managing the power of the same are provided. The non-volatile memory system includes a non-volatile memory configured to store a first mapping table comprising a list of a logical address and a physical address corresponding to the logical address with respect to a code region and a list of a logical address and a physical address corresponding to the logical address with respect to a general purpose (GP) region, and a controller configured to load the first mapping table from the non-volatile memory to a first memory and load the second mapping table from the non-volatile memory to a second memory. Power-up of the second memory is delayed with respect to power-up of the non-volatile memory system and the first or second memory is powered down if a condition is satisfied, so that power consumption of the non-volatile memory system is reduced.