Nonvolatile Memory Mirroring for Virtual Machine Live Migration

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In computer systems with byte-addressable nonvolatile memory, the persistence of virtual machine state in nonvolatile memory hinders features like live migration, fault tolerance, and high availability, which rely on shared storage systems.

Innovation Solution

Mirroring nonvolatile memory updates by flushing cache contents to a remote system, either synchronously or asynchronously, using memory addresses corresponding to NVM flush instructions, allowing for the replication of persistent state across systems.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If nonvolatile memory is used to store virtual machine state locally, then system performance and persistence are improved, but features like live migration, fault tolerance, and high availability deteriorate because persistent state cannot be shared across systems

Engineering Contradiction:
Improvesystem persistenceVSAvoidlive migration capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements remote copying of nonvolatile memory pages to a secondary system. When a page is modified in the local nonvolatile memory, the dirty bit is set and the page is copied to the remote system, enabling fault tolerance and live migration while maintaining local persistence performance.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent introduces a remote memory system as an intermediary that stores copies of nonvolatile memory pages. This mediator enables shared access and state replication between multiple systems without compromising the local nonvolatile memory's performance characteristics.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dirty bits in nonvolatile memory page table entries are not cleared until pages are remotely mirrored, then data consistency and fault tolerance are improved, but memory bandwidth and processing time worsen due to synchronous mirroring requirements

Engineering Contradiction:
Improvedata consistencyVSAvoidmemory access speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary actions by setting the dirty bit immediately when a page is modified, but delays the actual remote mirroring operation. This allows the system to prepare for consistency without immediately impacting performance, and the actual copying can be deferred or batched.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements periodic or batched remote mirroring operations rather than synchronous mirroring for every write. The dirty bits trigger mirroring operations that can be performed periodically or in batches, reducing the frequency and impact of remote memory operations while maintaining data consistency.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS10223026B2Consistent and efficient mirroring of nonvolatile memory state in virtualized environments where dirty bit of page table entries in non-volatile memory are not cleared until pages in non-volatile memory are remotely mirrored
Publication Date: 2019.03.05 VMWARE INC
  • US10223026B2 patent drawing
  • US10223026B2 patent drawing
  • US10223026B2 patent drawing

AI summary

Updates to nonvolatile memory pages are mirrored so that certain features of a computer system, such as live migration of applications, fault tolerance, and high availability, will be available even when nonvolatile memory is local to the computer system. Mirroring may be carried out when a cache flush instruction is executed to flush contents of the cache into nonvolatile memory. In addition, mirroring may be carried out asynchronously with respect to execution of the cache flush instruction by retrieving content that is to be mirrored from the nonvolatile memory using memory addresses of the nonvolatile memory corresponding to target memory addresses of the cache flush instruction.