Non-Volatile Memory Leakage Reduction via Negative Bias
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Solution Overview
Problem
Non-volatile memory arrays experience significant sub-threshold leakage during programming and erase operations, which increases the current load on the charge-pump, leading to potential memory operation failures and inefficiencies in terms of power consumption and chip area usage.
Innovation Solution
The introduction of a negative bias voltage is applied to the gate terminals of NMOS select and pull-down transistors to bias them into the accumulation region, reducing or eliminating sub-threshold leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional biasing is used during program and erase operations, then memory operations can be performed, but sub-threshold leakage current increases significantly
Solution Approach 1:
The patent applies a negative bias voltage to the gate terminal of the select transistor during program and erase operations, changing the electrical parameter (gate voltage) from conventional positive/zero bias to negative bias. This parameter change shifts the transistor operation mode to reduce sub-threshold leakage current while maintaining reliable memory operations. The negative bias voltage is specifically applied only during high-voltage operations to achieve leakage reduction without affecting normal read/write operations.
2Loss of energy
If higher voltage is applied to reduce leakage, then sub-threshold leakage is reduced, but power consumption increases
Solution Approach 1:
The patent applies negative bias voltage locally and selectively only to the gate terminal of the select transistor during specific high-voltage operations (program and erase), rather than applying voltage changes globally to the entire memory array or circuit. This localized application reduces leakage current at the critical select transistor level without unnecessarily increasing power consumption across the entire memory system. The negative bias is applied only when needed (during program/erase) and only to the specific transistor where leakage is problematic.
3Reliability
If charge-pump is designed to handle high leakage current, then memory operations are reliable, but chip area increases
Solution Approach 1:
The patent applies negative bias voltage to the select transistor gate terminal in advance during program and erase operations to prevent sub-threshold leakage current from occurring in the first place. This preliminary anti-action reduces the leakage current before it can accumulate and affect the charge-pump circuit, allowing the charge-pump to be designed for lower current handling capability and thus reducing the required chip area while maintaining operational reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces leakage current, making it easier for the charge-pump to handle the current load, thereby decreasing power consumption and chip area usage while allowing the same charge pump circuitry to be used across various memory densities and operating conditions.
Implementation Method 1
sub-threshold leakage current
Implementation Method 2
bias that transistor in the accumulation region
Implementation Method 3
The programming operation of the cell 10 utilizes the well-known Fowler-Nordheim (FN) tunneling effect. To perform FN-tunneling, high voltages are required which are generated on-chip through the charge-pump 32
Data Source
AI summary
A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.