Nonvolatile Memory Device Negative Well Voltage Control
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Solution Overview
Problem
Nonvolatile memory devices face challenges in maintaining reliability due to voltage differences between the well voltage and high supply voltage, which can lead to PN junction breakdown and affect data retention and programming accuracy.
Innovation Solution
The implementation of a method where a negative voltage is applied to the well of a transistor during specific intervals of the programming process, while varying the high supply voltage accordingly, to prevent DC path creation and maintain optimal voltage levels, thereby enhancing the reliability of the nonvolatile memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high supply voltage is applied to the channel of the transistor during programming, then programming speed and efficiency are improved, but the voltage difference between well and channel increases causing PN junction breakdown and reliability degradation
Solution Approach 1:
The patent applies dynamics by making the supply voltage variable rather than fixed. The supply voltage is dynamically adjusted based on the programming stage: a first high supply voltage is applied during the programming phase to ensure fast programming speed, and a second high supply voltage (lower than the first) is applied during the verify phase to prevent PN junction breakdown. This dynamic voltage adjustment resolves the contradiction between programming speed and reliability.
Solution Approach 2:
The patent implements periodic action through the ISPP (incremental step pulse programming) loop structure. Within each programming loop, the voltage is periodically switched between a first high level during programming and a second high level during verify operations. This periodic voltage switching allows the system to achieve both fast programming (during high voltage programming phases) and reliability protection (during verify phases with lower voltage), resolving the technical contradiction.
2Reliability
If a negative voltage is applied to the well during verify period, then PN junction breakdown is prevented and reliability is improved, but the voltage level must be carefully controlled to avoid affecting programming accuracy
Solution Approach 1:
The patent applies local quality by differentiating the voltage levels for different functional requirements. A first high supply voltage is used specifically for programming operations to ensure programming accuracy, while a second high supply voltage (lower than the first) is used specifically for verify operations to prevent PN junction breakdown. This localized voltage assignment to different operational phases resolves the contradiction between reliability and programming accuracy.
Solution Approach 2:
The patent implements preliminary action by performing verify operations with a lower second high supply voltage before the programming operation is fully complete. This preliminary verify at a safer voltage level allows the system to check programming status without risking PN junction breakdown, while the subsequent programming phase uses the higher first supply voltage to ensure accuracy. This sequential approach resolves the contradiction between reliability and precision.
Data Source
AI summary
A nonvolatile memory device (NVM), memory system and apparatus include control logic configured to perform a method of applying negative voltage on a selected wordline of the NVM. During a first time a first high voltage level is applied to the channel of a transistor of a address decoder and a ground voltage is applied to the well of the transistor. And, during a second time a second high voltage level is applied to the channel of the transistor, and within the second time interval a first negative voltage is applied to the well of the transistor. The first high voltage level is higher than the second high voltage level, and a voltage applied on the selected wordline is negative within the second time interval.