NVM On-Die Termination Circuit for High-Speed Signal Integrity
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Solution Overview
Problem
In high-speed storage devices, signal integrity between nonvolatile memory and controllers is critical for performance, but existing technologies lack effective methods to maintain signal integrity during high-speed operations, leading to increased command overhead and reduced performance.
Innovation Solution
The implementation of an on-die termination (ODT) circuit in nonvolatile memory devices, which determines ODT modes based on control signals and ODT signals received through dedicated pins, connects termination resistors to signal lines to prevent signal reflection, thereby enhancing signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If communication is performed at higher operation frequency to improve storage device speed, then productivity is improved, but signal integrity deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the termination resistance value based on the operating mode. The ODT circuit switches between first termination resistance (for read mode) and second termination resistance (for program/erase mode) to optimize signal integrity at different operation frequencies and modes, thereby resolving the contradiction between high-speed operation and signal integrity
Solution Approach 2:
The patent implements dynamics by making the termination resistance adjustable and mode-dependent rather than fixed. The ODT circuit transitions between different resistance states based on operation mode signals, enabling adaptive optimization of signal integrity for different communication frequencies and modes, thus resolving the contradiction between speed and reliability
2Reliability
If separate control signals are used for each memory chip to improve reliability, then device complexity increases
Solution Approach 1:
The patent applies universality by designing a single ODT circuit that can serve multiple memory chips through shared control mechanisms. The ODT control signal can be commonly applied to multiple chips, and the circuit can dynamically adjust termination resistance based on operation mode, eliminating the need for separate ODT control circuits for each chip while maintaining reliable operation
Solution Approach 2:
The patent merges the ODT control functionality into a unified circuit that can control multiple memory chips. By combining the ODT control signals and using a shared control mechanism, the patent reduces the overall number of control lines and circuitry required, thereby reducing device complexity while maintaining reliable operation across multiple chips
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves signal integrity and reduces command overhead, enhancing the performance of storage devices by allowing simultaneous transmission of commands and ODT signals, especially in multi-chip configurations.
Implementation Method 1
uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode
Data Source
AI summary
A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.