Non-volatile Memory Operation Window Expansion via Multi-cell Selection
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Solution Overview
Problem
Conventional non-volatile memory experiences a narrowing operation window due to increasing voltage offset over time, leading to low endurance, as the input current for accessing data is small and word lines enable memory cells row by row, resulting in low tolerance for voltage offset.
Innovation Solution
The implementation of a decoder to control word lines in non-volatile memory, allowing for two operation modes: simultaneous enabling of all word lines to increase current and endurance, and line-by-line enabling to adapt to different endurance and capacity requirements, using a multi-cells selection method to manage memory banks effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If word lines enable memory cells row by row, then data can be sequentially accessed to all memory cells, but the operation window narrows and endurance decreases due to small input current
Solution Approach 1:
The patent merges multiple memory cells (specifically 4 memory cells) into a single selection unit by connecting their bit lines together. This allows the cells to be selected simultaneously through a single word line activation, increasing the input current to 4 times that of a single cell and thereby expanding the operation window while maintaining sequential access capability at the bank level.
2Use of energy by moving object
If input current for accessing data is kept small, then power consumption is reduced, but voltage offset increases over time and operation window narrows
Solution Approach 1:
The patent introduces a dynamic selection mechanism where the memory is divided into multiple banks, and the number of cells selected per word line activation can be adjusted. By configuring different bank selection patterns, the system can dynamically adapt the current magnitude during operation, allowing optimization between power consumption and operation window based on application requirements.
3Reliability
If multiple bit lines are connected together, then current is increased and operation window is expanded, but device complexity increases
Solution Approach 1:
The patent segments the memory into multiple independent banks, where each bank contains a specific number of memory cells (e.g., 4 cells per bank). This segmentation allows the bit line connection complexity to be localized within each bank rather than spanning the entire memory array, making the complexity manageable and modular while still achieving current multiplication within each bank.
Data Source
AI summary
A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.