Non-volatile Memory Page Buffer Control for Data Collision Prevention
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Solution Overview
Problem
Non-volatile memory devices face data collision issues during asynchronous page mode operations, leading to increased data access time due to insufficient time synchronization, which can be exacerbated by the need for additional storage/output sequences to prevent collisions.
Innovation Solution
A non-volatile memory apparatus with a page buffer system that includes multiple buffer stages and a control unit capable of selectively activating these stages in a synchronous burst mode, allowing for increased data bandwidth by controlling the activation of buffer stages based on clock signals, thereby preventing data collisions and reducing access time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If asynchronous page mode is used to perform read/write operations, then data can be accessed in units of predetermined bits, but data collision occurs and data access time increases when continuous mode is performed
Solution Approach 1:
The page buffer is divided into multiple buffer stages (first buffer stage, second buffer stage, etc.), each capable of independently buffering data. This segmentation allows different buffer stages to handle different data transfer operations simultaneously, enabling continuous mode operation without data collision while maintaining asynchronous page mode functionality.
Solution Approach 2:
The control unit dynamically selects and activates appropriate buffer stages based on the operating mode (asynchronous page mode or continuous mode). In continuous mode, multiple buffer stages are activated to increase data bandwidth, while in asynchronous page mode, single buffer stage operation maintains simplicity. This dynamic adaptation resolves the contradiction between bandwidth and collision prevention.
2Reliability
If sufficient time is secured to prevent data collision during two accessing operations, then data collision is prevented, but data access time increases
Solution Approach 1:
Data is pre-buffered in multiple buffer stages before actual data transfer occurs. The control unit prepares the buffer stages in advance, so when continuous mode is initiated, data is already positioned and ready for immediate transfer, eliminating the need for additional time to prevent collisions during the transfer process.
Solution Approach 2:
Multiple buffer stages act as intermediaries between the memory array and the output interface. These intermediate buffers decouple the timing requirements of different accessing operations, allowing data to be transferred in continuous mode without requiring sufficient time gaps between operations, thus reducing data access time while preventing collisions.
3Ease of operation
If page buffers are equipped in correspondence with pages composed of predetermined cell arrays, then read/write operations can be performed, but additional storage/output sequences are needed to prevent data collision
Solution Approach 1:
The control unit automatically manages buffer stage selection and data transfer sequencing based on the operating mode. In continuous mode, the control unit self-manages the activation of multiple buffer stages and the coordination of data transfers without requiring external intervention or complex additional control sequences, simplifying the overall control while maintaining read/write capability.
Solution Approach 2:
The same page buffer structure with multiple buffer stages serves dual purposes: it enables both asynchronous page mode operations and continuous mode operations. The control unit universally manages both modes using the same hardware resources, eliminating the need for separate additional storage/output sequences for different operating modes.
Data Source
AI summary
A non-volatile memory apparatus for controlling a page buffer includes a page buffer configured to include a plurality of buffer stages, each buffering input/output data of cell arrays in units of predetermined number of bits, and a control unit configured to selectively activate one of the plurality of buffer stages when a burst mode as a synchronous mode is activated.