Non-Volatile Memory Page-Based Buffer Management
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Solution Overview
Problem
Flash memory devices face performance degradation and increased program/erase cycling due to the need to rewrite entire erase blocks for random write operations, which limits write speed and introduces delays, especially in devices with limited RAM and restricted program/erase cycles.
Innovation Solution
Implementing a method where logically erased physical blocks are allocated to a spare block pool and managed using a page-based buffer management scheme, allowing for efficient allocation and utilization of buffer blocks, and dynamically increasing overprovisioning to improve random write performance by using unused user space for caching and reducing the frequency of cleaning operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If block-based memory management is used to simplify controller operations, then ease of operation is improved, but write speed and productivity deteriorate due to frequent erase block rewriting
Solution Approach 1:
The patent segments memory management into two levels: block-based management for erase blocks (simplifying controller operations) and page-based management for data pages within blocks (enabling fine-grained updates). This segmentation allows the controller to maintain simple block-level tracking while implementing efficient page-level write operations that don't require complete block erasure and rewriting.
2Reliability
If entire erase blocks are rewritten for random write operations, then data integrity is maintained, but program/erase cycling increases and write speed decreases
Solution Approach 1:
The patent implements preliminary action by pre-erasing specific pages within an erase block before writing new data, rather than erasing the entire block. This allows the controller to prepare only the necessary pages for rewriting while leaving other pages intact, thereby maintaining data integrity for unwritten pages and significantly reducing the number of program/erase cycles required.
3Device complexity
If small RAM size is used to reduce device cost and size, then device complexity and cost are reduced, but memory management capability deteriorates
Solution Approach 1:
The patent extracts the complex page-level management functionality from the controller's RAM and implements it through firmware algorithms that operate on the flash memory structure itself. By taking out the need for large RAM-based page tables and implementing management logic in firmware, the system achieves sophisticated memory management with minimal RAM requirements, thus reducing device complexity while maintaining management capability.
Data Source
AI summary
A method of managing a non-volatile memory module, the method may include: allocating, by a memory controller, logically erased physical blocks of a non-volatile memory module to a spare block pool; allocating, by the memory controller, physical blocks from the spare block pool to become buffer blocks of a buffer of the non-volatile memory module; and controlling, by the memory controller, a utilization of the buffer blocks of the buffer by applying a page based buffer management scheme.