Non-Volatile Memory Page Programming Order Optimization
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Solution Overview
Problem
Current non-volatile semiconductor memory devices face challenges in achieving high write performance, as specified by industry standards, due to limitations in data transfer speeds and programming times.
Innovation Solution
The method involves programming logical pages of data in a specific order, where pages that take longer to program are prioritized first, allowing for parallel processing and reduced overall programming time, and utilizing a non-volatile storage system with single or dual row/column decoders and read/write circuits to manage memory arrays efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data is programmed in conventional order (lower page first, then upper page), then programming sequence is simple, but overall programming time increases
Solution Approach 1:
The patent applies preliminary action by receiving and buffering the upper logical page data before the lower logical page data, even though the lower page is programmed first. This allows the upper page to be ready in advance, enabling parallel processing operations and reducing the overall programming time while maintaining a simple programming sequence
2Ease of operation
If pages are programmed sequentially one after another, then programming order is simple to manage, but write performance is limited
Solution Approach 1:
The patent implements continuity of useful action by overlapping the buffering of second logical page data with the programming of the first logical page data. This parallel processing approach ensures that the memory device is continuously productive, improving write performance while maintaining manageable programming operations through systematic buffering and timing control
Data Source
AI summary
During a programming data transfer process in a non-volatile storage system, recording units of data are transferred from a host to a memory device, such as a memory card. For each recording unit, pages of data are arranged in an order such that a page which takes longer to write to a memory array of the memory device is provided before a page which takes less time to write. Overall programming time for the recording unit is reduced since a greater degree of parallel processing occurs. While the page which takes longer to program is being programmed to the memory array, the page which takes less time to program is being transferred to the memory device. After programming is completed, the memory device signals the host to transfer a next recording unit. The pages of data may include lower, middle and upper pages.